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參數(shù)資料
| 型號： | ADA4922-1ARDZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC DRIVER 18BIT DIFF 8-SOIC |
| 標準包裝： | 2,500 |
| 類型： | ADC 驅動器 |
| 應用： | 數(shù)據(jù)采集 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm Width）裸露焊盤 |
| 供應商設備封裝： | 8-SOIC-EP |
| 包裝： | 帶卷 (TR) |
ADA4922-1
Rev. 0 | Page 15 of 20
A more detailed view of the amplifier is shown in Figure 45.
Each amplifier is a 2-stage design that uses an input H-Bridge
followed by a rail-to-rail output stage (see Figure 46).
The architecture used in the ADA4922-1 results in excellent
SNR and distortion performance when compared to other
differential amplifiers.
RIN
MIRROR
C
OUTPUT
STAGE
MIRROR
INN
OUT
INP
I
05681-006
One of the more subtle points of operation arises when the two
amplifiers are used to generate the differential outputs. Because
the differential outputs are derived from a follower amplifier
and an inverting amplifier, they have different noise gains and,
therefore, different closed-loop bandwidths. For frequencies up
to 1 MHz, the bandwidth difference between outputs causes
little difference in the overall differential output performance.
However, because the bandwidth is the sum of both amplifiers,
the 3 dB point of the inverting amplifier defines the overall
differential 3 dB corner (see Figure 48).
0
1
10k
100M
05681-010
FREQUENCY (Hz)
CLOSED-LOOP
GAIN
–2
–4
–6
7
5
3
1M
100k
10M
DIFFERENTIAL OUTPUT
OUT+
OUT–
Figure 45. Internal Amplifier Architecture
ROUT
MIRROR
INTERNAL
REF
OUT
IN
I
05681-007
Figure 46. Output Stage Architecture
Figure 48. Closed-Loop AC Gain (Differential Outputs)
Figure 47 illustrates the open-loop gain and phase relationships
of each amplifier in the ADA4922-1.
Small delay and gain errors exist between the two outputs
because the inverting output is derived from the noninverting
output through an inverting amplifier. The gain error is due to
imperfect matching of the inverting amplifier gain and feedback
resistors, as well as differences in the transfer functions of the
two amplifiers, as illustrated in Figure 48. The delay error is due
to the delay through the inverting amplifier relative to the
noninverting amplifier output. The delay produces a reduction
in differential gain because the two outputs are not exactly 180°
out of phase. Both of these errors combine to produce an overall
gain error because the outputs are completely balanced. This
error is very small at the frequencies involved in most
ADA4922-1 applications.
125
–125
–100
–75
–50
–25
100
1k
10k
100M
05681-008
FREQUENCY (Hz)
M
A
GN
ITU
D
E
/PH
A
SE
(
d
B
/D
e
grees)
75
100
50
25
0
1M
100k
10M
GAIN
PHASE
Figure 47. Amplifier Gain/Phase Relationship
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| ADA4927-1YCPZ-R7 | 功能描述:IC OPAMP CF DIFF 65MA LN 16LFCSP RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標準包裝:2,500 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:- 轉換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:45nA 電壓 - 輸入偏移:2000µV 電流 - 電源:1.4mA 電流 - 輸出 / 通道:40mA 電壓 - 電源，單路/雙路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:14-TSSOP 包裝:帶卷 (TR) 其它名稱:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
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