參數(shù)資料
型號(hào): ADA4899-1
廠商: Analog Devices, Inc.
英文描述: Unity Gain Stable, Ultralow Distortion, 1 nV/ Hz Voltage Noise, High Speed Op Amp
中文描述: 單位增益穩(wěn)定,內(nèi)華達(dá)州超低失真1 / Hz的電壓噪聲,高速運(yùn)算放大器
文件頁數(shù): 5/20頁
文件大?。?/td> 496K
代理商: ADA4899-1
ADA4899-1
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Differential Input Voltage
Differential Input Current
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Rev. A | Page 5 of 20
Rating
12.6 V
See Figure 4
±1.2 V
±10 mA
–65°C to +150°C
–40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the ADA4899-1
package is limited by the associated rise in junction temperature
(T
J
) on the die. The plastic encapsulating the die locally reaches
the junction temperature. At approximately 150°C, which is the
glass transition temperature, the plastic changes its properties.
Even temporarily exceeding this temperature limit may change
the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4899-1.
Exceeding a junction temperature of 150°C for an extended
period can result in changes in silicon devices, potentially
causing failure.
The still-air thermal properties of the package and PCB (θ
JA
),
the ambient temperature (T
A
), and the total power dissipated in
the package (P
D
) determine the junction temperature of the die.
The junction temperature is calculated as
T
J
=
T
A
+ (
P
D
× θ
JA
)
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (V
S
) times the
quiescent current (I
S
). Assuming the load (R
L
) is referenced to
midsupply, the total drive power is V
S
/2 × I
OUT
, some of which is
dissipated in the package and some in the load (V
OUT
× I
OUT
).
The difference between the total drive power and the load
power is the drive power dissipated in the package.
P
D
=
Quiescent Power
+ (
Total Drive Power
Load Power
)
(
)
L
OUT
R
L
OUT
R
S
S
S
D
V
V
V
2
I
V
P
2
×
+
×
=
RMS output voltages should be considered. If R
L
is referenced to
V
S
–, as in single-supply operation, then the total drive power is
V
S
× I
OUT
. If the rms signal levels are indeterminate, consider the
worst case, when V
OUT
= V
S
/4 for R
L
to midsupply:
(
)
S
S
S
D
R
(
)
L
/
V
I
V
P
2
4
+
×
=
In single-supply operation with R
L
referenced to V
S
–, worst case
is V
OUT
= V
S
/2.
Airflow increases heat dissipation, effectively reducing θ
JA
. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduces the θ
JA
. Soldering the exposed paddle to the ground
plane significantly reduces the overall thermal resistance of the
package.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the exposed paddle
(e-pad) SOIC-8 (70°C/W) and LFCSP (70°C/W) packages on a
JEDEC standard 4-layer board. θ
JA
values are approximations.
0
AMBIENT TEMPERATURE (°C)
120
–40
–20
0
20
40
60
80
100
M
0.0
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
LFCSP AND SOIC
Figure 4. Maximum Power Dissipation vs. Ambient Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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