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參數(shù)資料
| 型號： | ADA4862-3 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Speed, G = +2, Low Cost, Triple Op Amp |
| 中文描述： | 高速，G \u003d 2時，低成本，三重運算放大器 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 262K |
| 代理商： | ADA4862-3 |
ADA4862-3
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature
Junction Temperature
Rev. A | Page 5 of 16
Rating
12.6 V
See Figure 3
±
V
S
65°C to +125°C
40°C to +105°C
JEDEC J-STD-20
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for device soldered in circuit board for surface-mount
packages.
Table 4. Thermal Resistance
Package Type
14-lead SOIC
Maximum Power Dissipation
The maximum safe power dissipation for the ADA4862-3 is
limited by the associated rise in junction temperature (T
J
) on
the die. At approximately 150
°
C, which is the glass transition
temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit may change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the amplifiers. Exceeding a
junction temperature of 150°C for an extended period can
result in changes in silicon devices, potentially causing
degradation or loss of functionality.
θ
JA
90
Unit
°C/W
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the die due
to the amplifier’s drive at the output. The quiescent power is the
voltage between the supply pins (V
S
) × the quiescent current (I
S
).
P
D
=
Quiescent Power
+ (
Total Drive Power
Load Power
)
(
)
L
OUT
R
L
OUT
R
S
S
S
D
V
V
V
2
I
V
P
2
–
×
+
×
=
RMS output voltages should be considered.
Airflow increases heat dissipation, effectively reducing θ
JA
.
In addition, more metal directly in contact with the package
leads and through holes under the device reduces θ
JA
.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 14-lead SOIC
(90°C/W) on a JEDEC standard 4-layer board. θ
JA
values are
approximations.
2.5
0
–55
AMBIENT TEMPERATURE (
°
C)
M
0
125
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115
2.0
1.5
1.0
0.5
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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