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參數(shù)資料
| 型號： | ADA4860-1 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Speed, Low Cost, Op Amp |
| 中文描述： | 高速，低成本，運算放大器 |
| 文件頁數(shù)： | 17/20頁 |
| 文件大?。?/td> | 660K |
| 代理商： | ADA4860-1 |
ADA4860-1
LAYOUT AND CIRCUIT BOARD PARASITICS
Careful attention to printed circuit board (PCB) layout prevents
associated board parasitics from becoming problematic and
affecting gain flatness and 3 dB bandwidth. In the printed
circuit environment, parasitics around the summing junction
(inverting input) or output pins can alter pulse and frequency
response. Parasitic capacitance can be unintentionally created
on a PC board via two parallel metal planes with a small vertical
separation (in FR4). To avoid parasitic problems near the
summing junction, signal line connections between the
feedback and gain resistors should be kept as short as possible
to minimize the inductance and stray capacitance. For similar
reasons, termination and load resistors should be located as
close as possible to the respective inputs. Removing the ground
plane on all layers from the area near and under the input and
output pins reduces stray capacitance.
Rev. 0 | Page 17 of 20
In a second test, 5.6 pF of capacitance was added directly at the
output of the gain = +2 amplifier. Figure 61 shows the results.
Extra output capacitive loading on the ADA4860-1 also causes
bandwidth extensions, as seen in Figure 61. The effect on the
gain = +2 circuit is more pronounced with lighter resistive
loading (1 kΩ). For pulse response behavior with added output
capacitances, see Figure 23, Figure 24, Figure 26, Figure 27,
Figure 29, Figure 30, Figure 32, and Figure 33.
3
–6
–5
–4
–3
–2
–1
1
2
0
1
100
10
1000
N
FREQUENCY (MHz)
0
V
= ±5V
G = +2
V
OUT
= 0.1V p-p
R
F
G
= 560
R
L
= 1k
, C
L
= 5.6pF EXTRA
R
L
= 100
, C
L
= 5.6pF EXTRA
R
L
= 1k
, C
L
= 0pF
R
L
= 100
, C
L
= 0pF
To illustrate the affects of parasitic capacitance, a small
capacitor of 0.4 pF from the amplifiers summing junction
(inverting input) to ground was intentionally added. This was
done on two boards with equal and opposite gains of +2 and 2.
Figure 60 reveals the effects of parasitic capacitance at the
summing junction for both noninverting and inverting gain
circuits. With gain = +2, the additional 0.4 pF of added
capacitance created an extra 43% 3 dB bandwidth extension,
plus some extra peaking. For gain = 2, a 5% increase in 3 dB
bandwidth was created with an extra 0.4 pF on summing
junction.
Figure 61. Small Signal Frequency Response vs. Output Capacitive Load
For more information on high speed board layout, go to:
www.analog.com
and
www.analog.com/library/analogDialogue/archives/39-
09/layout.html
.
1
–6
–5
–4
–3
–2
–1
0
1
100
10
1000
N
FREQUENCY (MHz)
0
V
S
= ±5V
V
OUT
= 0.1V p-p
R
L
G = +2, R
F
= 560
, C
J
= 0.4pF EXTRA
G = –2, R
F
= 402
, C
J
= 0.4pF EXTRA
G = –2, R
F
= 402
, C
J
= 0pF
G = +2, R
F
= 560
, C
J
= 0pF
Figure 60. Small Signal Frequency Response vs.
Added Summing Junction Capacitance
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| ADA4860-1YRJZ-RL7 | 功能描述:IC OPAMP CF LP 85MA SOT23-6 RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 產(chǎn)品培訓模塊:Differential Circuit Design Techniques for Communication Applications 標準包裝:1 系列:- 放大器類型:RF/IF 差分 電路數(shù):1 輸出類型:差分 轉(zhuǎn)換速率:9800 V/µs 增益帶寬積:- -3db帶寬:2.9GHz 電流 - 輸入偏壓:3µA 電壓 - 輸入偏移:- 電流 - 電源:40mA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VQFN 裸露焊盤，CSP 供應商設備封裝:16-LFCSP-VQ 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:551 (CN2011-ZH PDF) 其它名稱:ADL5561ACPZ-R7CT |
| ADA4861-3 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed, Low Cost, Triple Op Amp |
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