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參數(shù)資料
| 型號： | ADA4851-4 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Low Cost, High Speed, Rail-to-Rail, Output Op Amps |
| 中文描述： | 低成本，高速，軌到軌輸出運(yùn)算放大器 |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 325K |
| 代理商： | ADA4851-4 |
ADA4851-1/ADA4851-2/ADA4851-4
ABSOLUTE MAXIMUM RATINGS
Rev. D | Page 6 of 20
Table 4.
Parameter
Supply Voltage
Power Dissipation
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
Junction Temperature
Rating
12.6 V
See Figure 5
V
S
0.5 V to +V
S
+ 0.5 V
+V
S
to V
S
65°C to +125°C
40°C to +125°C
JEDEC J-STD-20
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for device soldered in circuit board for surface-mount
packages.
Table 5. Thermal Resistance
Package Type
6-lead SOT-23
14-lead TSSOP
8-lead MSOP
Maximum Power Dissipation
The maximum safe power dissipation for the ADA4851-1/
ADA4851-2/ADA4851-4 is limited by the associated rise in
junction temperature (T
J
) on the die. At approximately 150
°
C,
which is the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
amplifiers. Exceeding a junction temperature of 150°C for an
extended period can result in changes in silicon devices,
potentially causing degradation or loss of functionality.
θ
JA
170
120
150
Unit
°C/W
°C/W
°C/W
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the amplifiers’ drive at the output. The quiescent power
is the voltage between the supply pins (V
S
) times the quiescent
current (I
S
).
P
D
=
Quiescent Power
+ (
Total Drive Power
Load Power
)
(
)
L
OUT
R
L
OUT
R
S
S
S
D
V
V
V
2
I
V
P
2
–
×
+
×
=
RMS output voltages should be considered. If R
L
is referenced
to
V
S
, as in single-supply operation, the total drive power is
V
S
× I
OUT
. If the rms signal levels are indeterminate, consider the
worst case, when
V
OUT
=
V
S
/4 for
R
L
to midsupply.
(
)
S
S
S
D
R
(
)
L
V
I
V
P
2
4
+
×
=
In single-supply operation with
R
L
referenced to
V
S
, worst case
is
V
OUT
=
V
S
/2.
Airflow increases heat dissipation, effectively reducing θ
JA
.
Also, more metal directly in contact with the package leads and
through holes under the device reduces θ
JA
.
Figure 5 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 6-lead SOT-23
(170°C/W), the 8-lead MSOP (150°C/W), and the 14-lead
TSSOP (120°C/W) on a JEDEC standard 4-layer board. θ
JA
values are approximations.
0
–55
2.0
125
M
0
AMBIENT TEMPERATURE (
°
C)
1.5
1.0
0.5
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115
SOT-23-6
TSSOP
MSOP
Figure 5. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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