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參數(shù)資料
| 型號： | ADA4850-2 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Speed, Rail-to-Rail Output, Op Amp with Ultralow Power-Down |
| 中文描述： | 高速，軌到軌輸出運(yùn)算放大器與超低功耗降 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 303K |
| 代理商： | ADA4850-2 |
ADA4850-1/ADA4850-2
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Power Dissipation
Power Down Pin Voltage
Common-Mode Input Voltage
Differential Input Voltage
Storage Temperature
Operating Temperature Range
Lead Temperature Range
(Soldering 10 sec)
Junction Temperature
Rev. A | Page 5 of 16
Rating
12.6 V
See Figure 4
(V
S
+ 6) V
(V
S
0.5 ) V to (+V
S
+ 0.5) V
+V
S
to V
S
65°C to +125°C
40°C to +125°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θ
JA
is specified for the worst-case conditions, that is, θ
JA
is
specified for the device soldered in the circuit board for surface-
mount packages.
Table 4. Thermal Resistance
Package Type
16-Lead LFCSP
8-Lead LFCSP
Maximum Power Dissipation
The maximum safe power dissipation for the ADA4850-1/
ADA4850-2 is limited by the associated rise in junction
temperature (T
J
) on the die. At approximately 150
°
C, which is
the glass transition temperature, the plastic changes its
properties. Even temporarily exceeding this temperature limit
may change the stresses that the package exerts on the die,
permanently shifting the parametric performance of the
ADA4850-1/ADA4850-2. Exceeding a junction temperature of
150°C for an extended period of time can result in changes in
silicon devices, potentially causing degradation or loss of
functionality.
θ
JA
91
80
Unit
°C/W
°C/W
The power dissipated in the package (P
D
) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the ADA4850-1/ADA4850-2 drive at the output. The
quiescent power is the voltage between the supply pins (V
S
)
times the quiescent current (I
S
).
P
D
=
Quiescent Power
+ (
Total Drive Power
Load Power
)
(
)
L
OUT
R
L
OUT
R
S
S
S
D
V
V
V
2
I
V
P
2
–
×
+
×
=
RMS output voltages should be considered. If
R
L
is referenced
to
V
S
, as in single-supply operation, the total drive power is
V
S
× I
OUT
. If the rms signal levels are indeterminate, consider
the worst case, when
V
OUT
=
V
S
/4 for
R
L
to midsupply.
(
)
S
S
S
D
R
(
)
L
4
V
I
V
P
2
/
+
×
=
In single-supply operation with
R
L
referenced to
V
S
, the worst
case is
V
OUT
=
V
S
/2.
Airflow increases heat dissipation, effectively reducing θ
JA
.
Also, more metal directly in contact with the package leads and
exposed paddle from metal traces, through holes, ground, and
power planes reduce θ
JA
.
Figure 4 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the LFCSP (91°C/W)
package on a JEDEC standard 4-layer board. θ
JA
values are
approximations.
–55
125
–45 –35 –25 –15 –5
5
15 25 35
45 55 65 75 85 95 105 115
M
AMBIENT TEMPERATURE (
°
C)
0
0
2.5
2.0
1.5
1.0
0.5
LFCSP-8
LFCSP-16
Figure 4. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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