- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗6043 > ADA4841-2YRMZ (Analog Devices Inc)IC OPAMP VF R-R DUAL LP LN 8MSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | ADA4841-2YRMZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 11/21闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OPAMP VF R-R DUAL LP LN 8MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | 闆诲鍙嶉 |
| 闆昏矾鏁�(sh霉)锛� | 2 |
| 杓稿嚭椤炲瀷锛� | 婊挎摵骞� |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 13 V/µs |
| -3db甯跺锛� | 80MHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 3µA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 40µV |
| 闆绘祦 - 闆绘簮锛� | 1.2mA |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 60mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 2.7 V ~ 12 V锛�±1.35 V ~ 6 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 绠′欢 |
| 鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 | 768 (CN2011-ZH PDF) |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)鐣�(d膩ng)鍓嶇11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)
ADA4841-1/ADA4841-2
Rev. E | Page 18 of 20
Table 6. Recommended Values and Typical Performance
Gain
RF (惟)
RG (惟)
3 dB BW (MHz)
Slew Rate (V/渭s)
Peaking
(dB)
Output Noise ADA4841-1/
ADA4841-2 Only (nV/鈭欻z)
Total Output Noise
Including Resistors (nV/鈭欻z)
+1
0
N/A
77
12.5
0.9
2
+2
499
34
12.5
0.3
4
5.73
1
499
38
12.5
0.4
4
5.73
+5
499
124
11
12
0
10
11.9
+10
499
54.9
5
12
0
20
21.1
+20
499
26.1
2.3
11.2
0
40
42.2
Capacitor selection is critical for optimal filter performance.
Capacitors with low temperature coefficients, such as NPO
ceramic capacitors, are good choices for filter elements. Figure 51
shows the filter response.
05614-043
0.03
10
FREQUENCY (MHz)
1
0.1
鈥�40
GAIN
(
d
B)
鈥�35
鈥�30
鈥�25
鈥�20
鈥�15
鈥�10
鈥�5
0
5
Figure 51. Filter Frequency Response
LAYOUT CONSIDERATIONS
To ensure optimal performance, careful and deliberate attention
must be paid to the board layout, signal routing, power supply
bypassing, and grounding.
GROUND PLANE
It is important to avoid ground in the areas under and around
the input and output of the ADA4841-1/ADA4841-2. Stray
capacitance created between the ground plane and the input
and output pads of a device are detrimental to high speed
amplifier performance. Stray capacitance at the inverting input,
along with the amplifier input capacitance, lowers the phase
margin and can cause instability. Stray capacitance at the output
creates a pole in the feedback loop. This can reduce phase
margin and can cause the circuit to become unstable.
POWER SUPPLY BYPASSING
Power supply bypassing is a critical aspect in the performance
of the ADA4841-1/ADA4841-2. A parallel connection of
capacitors from each of the power supply pins to ground works
best. A typical connection is shown in Figure 49. Smaller value
capacitors offer better high frequency response where larger
value electrolytics offer better low frequency performance.
Paralleling different values and sizes of capacitors helps to
ensure that the power supply pins are provided a low ac impedance
across a wide band of frequencies. This is important for minimizing
the coupling of noise into the amplifier. This can be especially
important when the amplifier PSR is starting to roll off鈥攖he
bypass capacitors can help lessen the degradation in PSR
performance.
Starting directly at the ADA4841-1/ADA4841-2 power supply
pins, the smallest value capacitor should be placed on the same
side of the board as the amplifier, and as close as possible to the
amplifier power supply pin. The ground end of the capacitor
should be connected directly to the ground plane. Keeping the
capacitors鈥� distance short but equal from the load is important
and can improve distortion performance. This process should
be repeated for the next largest value capacitor.
It is recommended that a 0.1 渭F ceramic 0508 case be used. The
0508 case size offers low series inductance and excellent high
frequency performance. A 10 渭F electrolytic capacitor should be
placed in parallel with the 0.1 渭F capacitor. Depending on the
circuit parameters, some enhancement to performance can be
realized by adding additional capacitors. Each circuit is different
and should be individually analyzed for optimal performance.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| AD8066ARMZ | IC OPAMP VF R-R DUAL LN LP 8MSOP |
| AD8066ARZ | IC OPAMP VF R-R DUAL LN LP 8SOIC |
| AD8397ARDZ | IC OPAMP VF R-R DUAL LN 8SOIC |
| ADA4841-2YRZ | IC OPAMP VF R-R DUAL LP LN 8SOIC |
| AD8664ARZ | IC OPAMP GP R-R CMOS 4MHZ 14SOIC |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| ADA4841-2YRMZ-R7 | 鍔熻兘鎻忚堪:IC OPAMP VF R-R DUAL LP LN 8MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:100 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:- 杞�(zhu菐n)鎻涢€熺巼:0.2 V/µs 澧炵泭甯跺绌�:- -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:100pA 闆诲 - 杓稿叆鍋忕Щ:30µV 闆绘祦 - 闆绘簮:380µA 闆绘祦 - 杓稿嚭 / 閫氶亾:- 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):±2 V ~ 18 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SO 鍖呰:绠′欢 |
| ADA4841-2YRMZ-RL | 鍔熻兘鎻忚堪:IC OPAMP VF R-R DUAL LP LN 8MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:闆绘祦妾㈡脯(c猫) 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:- 杞�(zhu菐n)鎻涢€熺巼:- 澧炵泭甯跺绌�:125kHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:- 闆诲 - 杓稿叆鍋忕Щ:100µV 闆绘祦 - 闆绘簮:1.1µA 闆绘祦 - 杓稿嚭 / 閫氶亾:- 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):- 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:4-WFBGA锛孋SPBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:4-UCSP锛�2x2锛� 鍖呰:鍓垏甯� (CT) 鍏跺畠鍚嶇ū:MAX9634WERS+TCT |
| ADA4841-2YRZ | 鍔熻兘鎻忚堪:IC OPAMP VF R-R DUAL LP LN 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):4 杓稿嚭椤炲瀷:- 杞�(zhu菐n)鎻涢€熺巼:0.6 V/µs 澧炵泭甯跺绌�:1MHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:45nA 闆诲 - 杓稿叆鍋忕Щ:2000µV 闆绘祦 - 闆绘簮:1.4mA 闆绘祦 - 杓稿嚭 / 閫氶亾:40mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):3 V ~ 32 V锛�±1.5 V ~ 16 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-TSSOP锛�0.173"锛�4.40mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-TSSOP 鍖呰:甯跺嵎 (TR) 鍏跺畠鍚嶇ū:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
| ADA4841-2YRZ-R7 | 鍔熻兘鎻忚堪:IC OPAMP VF R-R DUAL LP LN 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:100 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:- 杞�(zhu菐n)鎻涢€熺巼:0.2 V/µs 澧炵泭甯跺绌�:- -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:100pA 闆诲 - 杓稿叆鍋忕Щ:30µV 闆绘祦 - 闆绘簮:380µA 闆绘祦 - 杓稿嚭 / 閫氶亾:- 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):±2 V ~ 18 V 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SO 鍖呰:绠′欢 |
| ADA4841-2YRZ-RL | 鍔熻兘鎻忚堪:IC OPAMP VF R-R DUAL LP LN 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:1 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:闆绘祦妾㈡脯(c猫) 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:- 杞�(zhu菐n)鎻涢€熺巼:- 澧炵泭甯跺绌�:125kHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:- 闆诲 - 杓稿叆鍋忕Щ:100µV 闆绘祦 - 闆绘簮:1.1µA 闆绘祦 - 杓稿嚭 / 閫氶亾:- 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):- 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:4-WFBGA锛孋SPBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:4-UCSP锛�2x2锛� 鍖呰:鍓垏甯� (CT) 鍏跺畠鍚嶇ū:MAX9634WERS+TCT |
鐧�(f膩)甯冪穵鎬ラ噰璩�(g貌u)锛�3鍒嗛悩宸﹀彸鎮ㄥ皣寰楀埌鍥炲京(f霉)銆�
