參數(shù)資料
型號: ADA4817-2ACPZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 10/28頁
文件大?。?/td> 0K
描述: IC OPAMP VF 410MHZ DUAL 16LFCSP
標準包裝: 5,000
系列: FastFET™
放大器類型: 電壓反饋
電路數(shù): 2
轉換速率: 870 V/µs
增益帶寬積: 410MHz
-3db帶寬: 1.05GHz
電流 - 輸入偏壓: 2pA
電壓 - 輸入偏移: 400µV
電流 - 電源: 19mA
電流 - 輸出 / 通道: 40mA
電壓 - 電源,單路/雙路(±): 5 V ~ 10 V,±2.5 V ~ 5 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 16-VQFN 裸露焊盤,CSP
供應商設備封裝: 16-LFCSP-VQ EP(4x4)
包裝: 帶卷 (TR)
ADA4817-1/ADA4817-2
Data Sheet
Rev. B | Page 18 of 28
LEAKAGE CURRENTS
Poor PCB layout, contaminants, and the board insulator
material can create leakage currents that are much larger than
the input bias current of the ADA4817-1/ADA4817-2. Any
voltage differential between the inputs and nearby runs sets
up leakage currents through the PCB insulator, for example, 1 V/
100 G = 10 pA. Similarly, any contaminants, such as skin oils
on the board, can create significant leakage. To reduce leakage
significantly, put a guard ring (shield) around the inputs and
input leads that are driven to the same voltage potential as the
inputs. This way there is no voltage potential between the inputs
and surrounding area to set up any leakage currents. For the
guard ring to be completely effective, it must be driven by a
relatively low impedance source and should completely
surround the input leads on all sides (above and below)
while using a multilayer board.
Another effect that can cause leakage currents is the charge
absorption of the insulator material itself. Minimizing the amount
of material between the input leads and the guard ring helps to
reduce the absorption. In addition, low absorption materials,
such as Teflon or ceramic, can be necessary in some instances.
INPUT CAPACITANCE
Along with bypassing and ground, high speed amplifiers can be
sensitive to parasitic capacitance between the inputs and ground. A
few picofarads of capacitance reduces the input impedance at high
frequencies, in turn increasing the gain of the amplifier, causing
peaking of the frequency response or even oscillations if severe
enough. It is recommended that the external passive components
connected to the input pins be placed as close as possible to the
inputs to avoid parasitic capacitance. The ground and power
planes must be kept at a small distance from the input pins on
all layers of the board.
INPUT-TO-INPUT/OUTPUT COUPLING
To minimize capacitive coupling between the inputs and outputs,
the output signal traces should not be parallel with the inputs.
In addition, the input traces should not be close to each other. A
minimum of 7 mils between the two inputs is recommended.
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