Full temperature range, VCC = 5 V, " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� ADA4320-1ACPZ-RL
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 12/16闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC LINE DVR CATV 5V 24LFCSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 5,000
鎳�(y墨ng)鐢細 CATV
杓稿嚭椤炲瀷锛� 宸垎
闆昏矾鏁�(sh霉)锛� 1
闆绘祦 - 闆绘簮锛� 260mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 4.75 V ~ 5.25 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 24-VFQFN 瑁搁湶鐒婄洡锛孋SP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 24-LFCSP-VQ EP锛�4x5锛�
鍖呰锛� 甯跺嵎 (TR)
ADA4320-1
Rev. A | Page 5 of 16
TIMING REQUIREMENTS
Full temperature range, VCC = 5 V, tR = tF = 4 ns, fCLK = 8 MHz, unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
Clock Pulse Width (tWH)
16
ns
Clock Period (tC)
32
ns
Setup Time SDATA vs. Clock (tDS)
5
ns
Setup Time DATEN vs. Clock (tES)
16
ns
Hold Time SDATA vs. Clock (tDH)
5
ns
Hold Time DATEN vs. Clock (tEH)
3
ns
Input 10% to 90% Rise and Fall Times, SDATA, DATEN, Clock
10
ns
VALID DATA-WORD G1
MSB...LSB
VALID DATA-WORD G2
SDATA
CLK
TXEN
ANALOG
OUTPUT
DATEN
tDS
tES
tEH
8 CLOCK CYCLES
GAIN TRANSFER (G1)
GAIN TRANSFER (G2)
tWH
tC
SIGNAL AMPLITUDE (p-p)
08
70
7-
0
02
Figure 2. Serial Interface Timing
SDATA MSB
MSB 鈥� 1
MSB 鈥� 2
CLK
VALID DATA BIT
tDS
tDH
08
70
7-
00
3
Figure 3. SDATA Timing
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