參數(shù)資料
型號(hào): AD9995KCPRL
廠商: ANALOG DEVICES INC
元件分類(lèi): 消費(fèi)家電
英文描述: 12-Bit CCD Signal Processor with Precision Timing ⑩ Generator
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC56
封裝: 8 X 8 MM, MO-220-VLLD-2, LFCSP-56
文件頁(yè)數(shù): 45/60頁(yè)
文件大?。?/td> 1593K
代理商: AD9995KCPRL
AD9995
–45–
Table XXIX. V-Pattern Group 3 (VPAT3) Register Map (continued)
Data Bit Default
Address Content
26
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register Name
V1TOG3_3
V2TOG1_3
V2TOG2_3
V2TOG3_3
V3TOG1_3
V3TOG2_3
V3TOG3_3
V4TOG1_3
V4TOG2_3
V4TOG3_3
V5TOG1_3
V5TOG2_3
V5TOG3_3
V6TOG1_3
V6TOG2_3
V6TOG3_3
FREEZE1_3
RESUME1_3
FREEZE2_3
RESUME2_3
Description
V1 Toggle Position 3
V2 Toggle Position 1
V2 Toggle Position 2
V2 Toggle Position 3
V3 Toggle Position 1
V3 Toggle Position 2
V3Toggle Position 3
V4 Toggle Position 1
V4 Toggle Position 2
V4 Toggle Position 3
V5 Toggle Position 1
V5 Toggle Position 2
V5 Toggle Position 3
V6 Toggle Position 1
V6 Toggle Position 2
V6 Toggle Position 3
V1–V6 Freeze Position 1
V1–V6 Resume Position 1
V1–V6 Freeze Position 2
V1–V6 Resume Position 2
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
27
28
29
2A
2B
2C
2D
2E
2F
Table XXX. V-Pattern Group 4 (VPAT4) Register Map
Data Bit Default
Address Content
30
Value
0
0
0
Register Name
VPOL_4
UNUSED
VPATLEN_4
Description
VPAT4 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
Unused.
Total Length of VPAT4. Note: If using VPAT4 as a second V-sequence in
the VSG active line, this value is the start position for the second V-sequence.
V1 Toggle Position 1
V1 Toggle Position 2
V1 Toggle Position 3
V2 Toggle Position 1
V2 Toggle Position 2
V2 Toggle Position 3
V3 Toggle Position 1
V3 Toggle Position 2
V3Toggle Position 3
V4 Toggle Position 1
V4 Toggle Position 2
V4 Toggle Position 3
V5 Toggle Position 1
V5 Toggle Position 2
V5 Toggle Position 3
V6 Toggle Position 1
V6 Toggle Position 2
V6 Toggle Position 3
V1–V6 Freeze Position 1
V1–V6 Resume Position 1
V1–V6 Freeze Position 2
V1–V6 Resume Position 2
[5:0]
[11:6]
[23:12]
31
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
[11:0]
[23:12]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
V1TOG1_4
V1TOG2_4
V1TOG3_4
V2TOG1_4
V2TOG2_4
V2TOG3_4
V3TOG1_4
V3TOG2_4
V3TOG3_4
V4TOG1_4
V4TOG2_4
V4TOG3_4
V5TOG1_4
V5TOG2_4
V5TOG3_4
V6TOG1_4
V6TOG2_4
V6TOG3_4
FREEZE1_4
RESUME1_4
FREEZE2_4
RESUME2_4
32
33
34
35
36
37
38
39
3A
3B
REV. 0
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