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參數(shù)資料
| 型號： | AD9984APCBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance 10-Bit Display Interface |
| 中文描述： | 高性能10位顯示接口 |
| 文件頁數(shù)： | 27/44頁 |
| 文件大?。?/td> | 490K |
| 代理商： | AD9984APCBZ |
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AD9984A
Hex
Address
Rev. 0 | Page 27 of 44
Read/Write,
Read Only
Bits
2
Default
Value
**** *0**
Register Name
Description
Power-Down Pin Polarity. Sets the polarity of the signal on the
PWRDN pin.
0 = PWRDN polarity is negative.
1 = PWRDN polarity is positive.
Power-Down Fast Switching Control.
0 = Normal power-down operation.
1 = The chip stays powered up, and the outputs are put in high
impedance mode.
SOGOUT High Impedance Control.
0 = SOGOUT operates as normal during power-down.
1 = SOGOUT is in high impedance during power-down.
Output Mode.
100 = 4:4:4 RGB mode.
101 = 4:2:2 YCbCr mode.
110 = 4:4:4 DDR mode.
Primary Output Enable.
0 = Primary output is in high impedance state.
1 = Primary output is enabled.
Secondary Output Enable.
0 = Secondary output is in high impedance state.
1 = Secondary output is enabled.
Output Drive Strength. Applies to all outputs except VSOUT.
00 = Low output drive strength.
01 = Medium output drive strength.
1x = High output drive strength.
Output Clock Invert. Applies to all clocks output on DATACK.
0 = Noninverted Pixel Clock.
1 = Inverted Pixel Clock.
Output Clock Select.
00 = Pixel clock.
01 = 90° phase-shifted pixel clock.
10 = 2× pixel clock.
11 = 0.5× pixel clock.
Output High Impedance.
0 = Normal outputs.
1 = All outputs except SOGOUT in high impedance mode.
SOGOUT High Impedance.
0 = Normal drive.
1 = SOGOUT pin is in high impedance mode.
Field Output Polarity. Sets the polarity of the field output signal.
0 = Active low is an even field, active high is an odd field.
1 = Active low is an odd field, active high is an even field.
PLL Sync Filter Enable.
0 = PLL uses raw HSYNCx/SOGINx.
1 = PLL uses filtered Hsync/SOG.
Sync Processing Input Select. Selects the sync source for the sync
processor.
0 = Sync processing uses raw HSYNCx/SOGINx.
1 = Sync processing uses regenerated Hsync from sync filter.
Must be set to 1 for proper operation.
Must be set to default for proper operation.
Must be set to default for proper operation.
Sets the window of time around the regenerated Hsync leading
edge (in 25 ns steps) that sync pulses are allowed to pass through.
HSYNC0 Detection.
0 = HSYNC0 is not active.
1 = HSYNC0 is active.
1
**** **0*
0
**** ***0
0x1F
R/W
7:5
100* ****
Output Select 1
4
***1 ****
3
**** 0***
2:1
**** *10*
0
**** ***0
0x20
R/W
7:6
0*** ****
Output Select 2
5
*0** ****
4
**0* ****
3
***0 ****
2
**** 1***
1
**** *0**
0x21
0x22
0x23
R/W
R/W
R/W
0
7:0
7:0
7:0
**** ***0
0010 0000
0011 0010
0000 1010
Sync Filter Window
Width
Sync Detect
0x24
RO
7
_*** ****
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