參數(shù)資料
型號(hào): AD9984AKSTZ-140
廠商: Analog Devices Inc
文件頁(yè)數(shù): 22/44頁(yè)
文件大?。?/td> 0K
描述: IC DISPLAY 10BIT 140MSPS 80LQFP
標(biāo)準(zhǔn)包裝: 1
類型: 接口
應(yīng)用: 顯示器,處理,電視
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(14x14)
包裝: 托盤
AD9984A
Rev. 0 | Page 29 of 44
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
4
***0 ****
Auto-Offset Hold.
Disables the auto-offset and holds the feedback result.
0 = Continuous update.
1 = One time update.
3:0
**** 0000
Must be written to default for proper operation.
0x2D
R/W
7:0
1111 0000
Test Register 5
Must be written to 0xE8 for proper operation.
0x2E
R/W
7:0
1111 0000
Test Register 6
Must be written to 0xE0 for proper operation.
0x34
R/W
2
**** *0**
SOG Filter
SOG Filter Enable. When enabled, filters out SOG inputs less than 250 ns.
0 = SOG filter disabled.
1 = SOG filter enabled.
0x36
R/W
0
**** ***0
VCO Gear
VCO Gear Select. Adds another range to the VCO. Used for lower
frequencies only.
0 = Disable low VCO gear.
1 = Enable low VCO gear.
0x3C
R/W
7:4
0000 ****
Auto Gain
Test Bits. Must be set to default for proper operation.
3
**** 0***
Auto Gain Matching Hold.
0 = Disables auto gain updates and holds the current auto offset values.
1 = Allows auto gain to continuously update.
2:0
**** *000
Auto Gain Matching Enable.
000 = Auto gain matching is disabled.
110= Auto gain matching is enabled.
1 Functions with more than eight control bits, such as PLL divide ratio, gain, and offset, are only updated when the LSBs are written to (for example, Register 0x02 for
PLL divide ratio).
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