參數(shù)資料
型號(hào)： AD9984AKSTZ-140
廠商： ANALOG DEVICES INC
元件分類： 其它接口
英文描述： High Performance 10-Bit Display Interface
中文描述： SPECIALTY INTERFACE CIRCUIT, PQFP80
封裝： ROHS COMPLIANT, MS-026BEC, LQFP-80
文件頁數(shù)： 14/44頁
文件大?。?/td> 490K
代理商： AD9984AKSTZ-140
AD9984A
CLOCK GENERATION
A PLL is used to generate the pixel clock. The Hsync input
provides a reference frequency to the PLL. A voltage controlled
oscillator (VCO) generates a much higher pixel clock frequency.
The pixel clock is divided by the PLL divide value (Register 0x01
and Register 0x02) and phase-compared with the Hsync input.
Any error is used to shift the VCO frequency and maintain lock
between the two signals.
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,
the signal slews from the old pixel amplitude and settles at its
new value; this is called the slewing time. Then, the input voltage
stabilizes before the signal must slew to a new value; this is called
the stable time. The ratio of the slewing time to the stable time is
a function of the graphics DAC bandwidth and the bandwidth
of the transmission system (cable and termination). This ratio is
also a function of the overall pixel rate. If the dynamic charac-
teristics of the system remain fixed, the slewing and settling
time is likewise fixed. This time must be subtracted from the
total pixel period, leaving the stable period. At higher pixel
frequencies, the total cycle time is shorter and the stable pixel
time becomes shorter as well.
Rev. 0 | Page 14 of 44
PIXEL CLOCK
INVALID SAMPLE TIMES
0
Figure 7. Pixel Sampling Times
Any jitter in the clock reduces the precision of the sampling
time and it must also be subtracted from the stable pixel time.
Considerable care has been taken in the design of the AD9984A
clock generation circuit to minimize jitter. The clock jitter of the
AD9984A is low in all operating modes, making the reduction
in the valid sampling time due to jitter negligible.
The PLL characteristics are determined by the loop filter design,
the PLL charge pump current, and the VCO range setting. The
loop filter design is illustrated in Figure 8. Recommended settings
of the VCO range and charge pump current for VESA standard
display modes are listed in Table 10.
C
P
8.2nF
C
82nF
R
Z
1.5k
FILT
PV
D
0
Figure 8. PLL Loop Filter Design
Four programmable registers are provided to optimize the
performance of the PLL. These registers are the 12-bit divisor
register, the 2-bit VCO range register, the 3-bit charge pump
current register, and the 5-bit phase adjust register.
The 12-Bit Divisor Register
The input Hsync frequencies can accommodate any Hsync as
long as the product of the Hsync and the PLL divisor falls
within the operating range of the VCO. The PLL multiplies the
frequency of the Hsync signal, producing pixel clock frequencies
in the range of 10 MHz to 170 MHz. The divisor register controls
the exact multiplication factor. This register can be set to any
value between 2 and 4095 as long as the output frequency is
within range.
The 2-Bit VCO Range Register
To improve the noise performance of the AD9984A, the VCO
operating frequency range is divided into four overlapping
regions. The VCO range register sets this operating range. The
frequency ranges for the four regions are shown in Table 8.
Table 8. VCO Frequency Ranges
PV1
PV0
Pixel Clock Range (MHz)
0
0
10 to 31
1
0
1
31 to 62
1
0
62 to 124
1
1
124 to 170
KVCO Gain (MHz/V)
150
150
150
150
1
For frequencies of 18 MHz or lower, enable the VCO low range bit (Reg. 0x36[0]).
The 3-Bit Charge Pump Current Register
This register varies the current that drives the low-pass loop
filter. The possible current values are listed in Table 9.
Table 9. Charge Pump Current/Control Bits
Ip2
Ip1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Ip0
0
1
0
1
0
1
0
1
Current (μA)
50
100
150
250
350
500
750
1500
The 5-Bit Phase Adjust Register
The phase of the generated sampling clock can be shifted to
locate an optimum sampling point within a clock cycle. The
phase adjust register provides 32 phase-shift steps of 11.25°
each. The Hsync signal with an identical phase shift is available
through the HSOUT pin. Phase adjust is still available if an
external pixel clock is used. The COAST pin or the internal
coast is used to allow the PLL to continue to run at the same
frequency in the absence of the incoming Hsync signal or
during disturbances in Hsync (such as from equalization
pulses). This can be used during the vertical sync period or at
any other time that the Hsync signal is unavailable.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9984AKSTZ-170 功能描述:IC DISPLAY 10BIT 170MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064
AD9984APCBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 10-Bit Display Interface
AD9984KSTZ-110 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9984KSTZ-140 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:
AD9984KSTZ-170 制造商:Analog Devices 功能描述:
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