參數(shù)資料
型號(hào): AD9984AKCPZ-170
廠商: ANALOG DEVICES INC
元件分類(lèi): 其它接口
英文描述: High Performance 10-Bit Display Interface
中文描述: SPECIALTY INTERFACE CIRCUIT, QCC64
封裝: 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁(yè)數(shù): 25/44頁(yè)
文件大?。?/td> 490K
代理商: AD9984AKCPZ-170
AD9984A
Hex
Address
Rev. 0 | Page 25 of 44
Read/Write,
Read Only
Bits
6
Default
Value
*0** ****
Register Name
Description
Hsync Source Select. Determines the source of the Hsync for PLL and
sync processing. This bit is used only if Reg. 0x12, Bit 7 is set to 1 or if
both syncs are active.
0 = Hsync is from HSYNCx input pin.
1 = Hsync is from SOG.
Hsync Input Polarity Override.
0 = The chip selects the Hsync input polarity.
1 = The input polarity of Hsync is controlled by Reg. 0x12, Bit 4.
Hsync Input Polarity. This bit is used only if Reg. 0x12, Bit 5 is set to 1.
0 = Hsync input polarity is negative.
1 = Hsync input polarity is positive.
Hsync Output Polarity. Sets the polarity of the Hsync output signal
(HSOUT).
0 = HSOUT polarity is negative.
1 = HSOUT polarity is positive.
Sets the number of pixel clocks that HSOUT is active.
Vsync Source Override.
0 = The chip determines the active Vsync source.
1 = The active Vsync source is set by Reg. 0x14, Bit 6.
Vsync Source Select. Determines the source of Vsync for sync
processing. This bit is used only if Reg. 0x14, Bit 7 is set to 1.
0 = Vsync is from the VSYNCx input pin.
1 = Vsync is from the sync separator.
Vsync Input Polarity Override.
0 = The chip selects Vsync input polarity.
1 = The input polarity of Vsync is set by Reg. 0x14, Bit 4.
Vsync Input Polarity. This bit is used only if Reg. 0x14, Bit 5 is set to 1.
0 = Vsync input polarity is negative.
1 = Vsync input polarity is positive.
Vsync Output Polarity. Sets the polarity of the output Vsync signal
(VSOUT).
0 = VSOUT polarity is negative.
1 = VSOUT polarity is positive.
Vsync Filter Enable. This needs to be enabled when using the Hsync
to Vsync counter.
0 = The Vsync filter is disabled.
1 = The Vsync filter is enabled.
Vsync Duration Block Enable. This is designed to be used with the
Vsync filter.
0 = Vsync output duration is unchanged.
1 = Vsync output duration is set by Register 0x15.
Sets the number of Hsyncs that Vsync out is active. This is only used if
Reg. 0x14, Bit 1 is set to 1.
The number of Hsync periods to coast prior to Vsync.
The number of Hsync periods to coast after Vsync.
Coast Source. Determines the source of the coast signal.
0 = Using internal coast generated from Vsync.
1 = Using external coast signal from COAST pin.
Coast Polarity Override.
0 = The chip selects the coast polarity.
1 = The polarity of the coast signal is set by Reg. 0x18, Bit 5.
Coast Polarity. This bit is used only if Reg. 0x18, Bit 6 is set to 1.
0 = Coast polarity is negative.
1 = Coast polarity is positive.
Clamp Source Select. Determines the source of the clamp timing.
0 = Uses the internal clamp generated from Hsync.
1 = Uses the external CLAMP signal.
5
**0* ****
4
***1 ****
3
**** 1***
0x13
0x14
R/W
R/W
7:0
7
0010 0000
0*** ****
Hsync Duration
Vsync Control
6
*0** ****
5
**0* ****
4
***1 ****
3
**** 1***
2
**** *0**
1
**** **0*
0x15
R/W
7:0
0000 1010
Vsync Duration
0x16
0x17
0x18
R/W
R/W
R/W
7:0
7:0
7
0000 0000
0000 0000
0*** ****
Precoast
Postcoast
Coast and Clamp
Control
6
*0** ****
5
**1* ****
4
***0 ****
相關(guān)PDF資料
PDF描述
AD9984AKSTZ-140 High Performance 10-Bit Display Interface
AD9984AKSTZ-170 High Performance 10-Bit Display Interface
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AD9985A 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
AD9985ABSTZ-110 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
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