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參數(shù)資料
| 型號(hào)： | AD9984AKCPZ-140 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DISPLAY 10BIT 140MSPS 64LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 接口 |
| 應(yīng)用： | 顯示器，處理，電視 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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AD9984A
Rev. 0 | Page 27 of 44
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
2
**** *0**
Power-Down Pin Polarity. Sets the polarity of the signal on the
PWRDN pin.
0 = PWRDN polarity is negative.
1 = PWRDN polarity is positive.
1
**** **0*
Power-Down Fast Switching Control.
0 = Normal power-down operation.
1 = The chip stays powered up, and the outputs are put in high
impedance mode.
0
**** ***0
SOGOUT High Impedance Control.
0 = SOGOUT operates as normal during power-down.
1 = SOGOUT is in high impedance during power-down.
0x1F
R/W
7:5
100* ****
Output Select 1
Output Mode.
100 = 4:4:4 RGB mode.
101 = 4:2:2 YCbCr mode.
110 = 4:4:4 DDR mode.
4
***1 ****
Primary Output Enable.
0 = Primary output is in high impedance state.
1 = Primary output is enabled.
3
**** 0***
Secondary Output Enable.
0 = Secondary output is in high impedance state.
1 = Secondary output is enabled.
2:1
**** *10*
Output Drive Strength. Applies to all outputs except VSOUT.
00 = Low output drive strength.
01 = Medium output drive strength.
1x = High output drive strength.
0
**** ***0
Output Clock Invert. Applies to all clocks output on DATACK.
0 = Noninverted Pixel Clock.
1 = Inverted Pixel Clock.
0x20
R/W
7:6
0*** ****
Output Select 2
Output Clock Select.
00 = Pixel clock.
01 = 90° phase-shifted pixel clock.
10 = 2× pixel clock.
11 = 0.5× pixel clock.
5
*0** ****
Output High Impedance.
0 = Normal outputs.
1 = All outputs except SOGOUT in high impedance mode.
4
**0* ****
SOGOUT High Impedance.
0 = Normal drive.
1 = SOGOUT pin is in high impedance mode.
3
***0 ****
Field Output Polarity. Sets the polarity of the field output signal.
0 = Active low is an even field, active high is an odd field.
1 = Active low is an odd field, active high is an even field.
2
**** 1***
PLL Sync Filter Enable.
0 = PLL uses raw HSYNCx/SOGINx.
1 = PLL uses filtered Hsync/SOG.
1
**** *0**
Sync Processing Input Select. Selects the sync source for the sync
processor.
0 = Sync processing uses raw HSYNCx/SOGINx.
1 = Sync processing uses regenerated Hsync from sync filter.
0
**** ***0
Must be set to 1 for proper operation.
0x21
R/W
7:0
0010 0000
Must be set to default for proper operation.
0x22
R/W
7:0
0011 0010
Must be set to default for proper operation.
0x23
R/W
7:0
0000 1010
Sync Filter Window
Width
Sets the window of time around the regenerated Hsync leading
edge (in 25 ns steps) that sync pulses are allowed to pass through.
0x24
RO
7
_*** ****
Sync Detect
HSYNC0 Detection.
0 = HSYNC0 is not active.
1 = HSYNC0 is active.
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| AD9984AKCPZ-170 | 功能描述:IC DISPLAY 10BIT 170MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD9984AKSTZ-140 | 功能描述:IC DISPLAY 10BIT 140MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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| AD9984APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 10-Bit Display Interface |
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