![](http://datasheet.mmic.net.cn/310000/AD9983AKSTZ-140_datasheet_16240217/AD9983AKSTZ-140_28.png)
AD9983A
Preliminary Technical Data
Hex
Address
0x23
Rev. PrA | Page 28 of 44
Read/Write,
Read Only
R/W
Bits
7:0
Default
Value
0000 1010
Register Name
Sync Filter
Window Width
Sync Detect
Description
Sets the window of time around the regenerated Hsync leading
edge (in 25 ns steps) that sync pulses are allowed to pass through.
HSYNC0 Detection Bit.
0 = HSYNC0 is not active
1 = HSYNC0 is active
HSYNC1 Detection Bit.
0 = HSYNC1 is not active
1 = HSYNC1 is active
VSYNC0 Detection Bit.
0 = VSYNC0 is not active
1 = VSYNC0 is active
VSYNC1 Detection Bit.
0 = VSYNC1 is not active
1 = VSYNC1 is active
SOGIN0 Detection Bit
0 = SOGIN0 is not active
1 = SOGIN0 is active
SOGIN1 Detection Bit
0 = SOGIN1 is not active
1 = SOGIN1 is active
COAST Detection Bit.
0 = External COAST is not active
1 = External COAST is active
CLAMP Detection Bit.
0 = External CLAMP is not active
1 = External CLAMP is active
HSYNC0 Polarity.
0 = HSYNC0 polarity is active low
1 = HSYNC0 polarity is active high
HSYNC1 Polarity.
0 = HSYNC1 polarity is active low
1 = HSYNC1 polarity is active high
VSYNC0 Polarity.
0 = VSYNC0 polarity is active low
1 = VSYNC0 polarity is active high
VSYNC1 Polarity.
0 = VSYNC1 polarity is active low
1 = VSYNC1 polarity is active high
COAST Polarity.
0 = External COAST polarity is active low
1 = External COAST polarity is active high
CLAMP Polarity.
0 = External CLAMP polarity is active low
1 = External CLAMP polarity is active high
Extraneous Pulses Detected.
0 = No extraneous pulses detected on HSYNCx
1 = Extraneous pulses detected on HSYNCx
Sync Filter Lock
0 = Sync filter unlocked
1 = Sync filter locked
MSBs of Hsyncs per Vsync count.
0x24
RO
7
_*** ****
6
*_** ****
5
**_* ****
4
***_ ****
3
**** _***
2
**** *_**
1
**** **_*
0
**** ***_
0x25
RO
7
_*** ****
Sync Polarity
Detect
6
*_** ****
5
**_* ****
4
***_ ****
3
**** _***
2
**** *_**
1
**** **_*
0
0x26
RO
7:0
Hsyncs Per Vsync
MSBs
Hsyncs Per Vsync
LSBs
TestReg1
TestReg2
TestReg3
TestReg4
0x27
RO
7:4
LSBs of Hsyncs per Vsync count.
0x28
0x29
0x2A
0x2B
R/W
R/W
RO
RO
7:0
7:0
7:0
7:0
1011 1111
0000 0010
Must be written to Reg. 0xBF for proper operation.
Must be written to Reg. 0x02 for proper operation.
Read-only bits for future use.
Read-only bits for future use.