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參數(shù)資料
| 型號： | AD9981KSTZ-80 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | High Performance 10-Bit Display Interface |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT |
| 文件頁數(shù)： | 34/44頁 |
| 文件大?。?/td> | 506K |
| 代理商： | AD9981KSTZ-80 |
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AD9981
Preliminary Technical Data
0x1B
Rev. 0 | Page 34 of 44
7
Clamp Polarity Override
This bit is used to override the internal circuitry that
determines the polarity of the clamp signal. The
power-up default setting is 0.
Table 35. Clamp Polarity Override Settings
Override Bit
Result
0
Clamp Polarity Determined by Chip
1
Clamp Polarity Determined by User
Register 0x1B, Bit 6
0x1B
6
Input Clamp Polarity
This bit indicates the polarity of the clamp signal only
if Bit 7 of Register 0x1B = 1. The power-up default
setting is 1.
Table 36. Clamp Polarity Override Settings
CLMPOL
Result
0
Active low
1
Active high
0x1B
5
Auto-Offset Enable
This bit selects between auto-offset mode and manual
offset mode (auto-offset disabled). See the section on
auto-offset operation. The power-up default setting
is 0.
Table 37. Auto-Offset Settings
Auto-Offset
Result
0
Auto-offset is disabled
1
Auto-offset is enabled (manual offset mode)
0x1B
4:3
Auto-Offset Update Frequency
These bits control how often the auto-offset circuit is
updated (if enabled). Updating every 64 Hsyncs is
recommended. The power-up default setting is 11.
Table 38. Auto-Offset Update Mode
Clamp Update
Result
00
Update offset every clamp period
01
Update offset every 16 clamp periods
10
Update offset every 64 clamp periods
11
Update offset every Vsync periods
0x1B
2-0
Must be written to 011 for proper operation.
SOG CONTROL
0x1D
7:3
SOG Comparator Threshold
This register allows the comparator threshold of the
SOG slicer to be adjusted. This register adjusts it in
steps of 8 mV, with the minimum setting equaling
8 mV and the maximum setting equaling 256 mV. The
power-up default setting is 15 DDR and corresponds
to a threshold value of 128 mV.
0x1D
2
SOG Output Polarity
This bit sets the polarity of the SOGout signal. The
power-up default setting is 0.
Table 39. SOGOUT Polarity Settings
SOGOUT
Result
0
Active low
1
Active high
0x1D
1:0
SOG Output Select
These register bits control what is output on the
SOGOUT pin. Options are the raw SOG from the
slicer (this is the unprocessed SOG signal produced
from the sync slicer), the raw Hsync, the regenerated
sync from the sync filter which can generate missing
syncs either due to coasting or drop-out, or finally the
filtered sync which excludes extraneous syncs not
occurring within the sync filter window. The power-
up default setting is 0.
Table 40. SOGOUT Polarity Settings
SOGOUT Select
Function
00
Raw SOG from sync slicer (SOG0 or SOG1)
01
Raw Hsync (HSYNC0 or HSYNC1)
10
Regenerated Sync from sync filter
11
Filtered sync from sync filter
INPUT AND POWER CONTROL
0x1E
7
Channel Select Override
This bit provides an override to the automatic input
channel selection. Power-up default setting is 0.
Table 41. Channel Source Override
Override
Result
0
Channel input source determined by chip
1
Channel input source determined by user
Register 0x1E, Bit 6
0x1E
6
Channel Select
This bit selects the active input channel if
Register 0x1E, bit 7 = 1. This selects between
Channel 0 data and syncs or Channel 1 data and
syncs. Power-up default setting is 0.
Table 42. Channel Select
Channel Select
Result
0
Channel 0 data and syncs are selected
1
Channel 1 data and syncs are selected
0x1E
5
Programmable Bandwidth
This bit selects between a low or high input band-
width. It is useful in limiting noise for lower frequency
inputs. The power-up default setting is 1. Low analog
input bandwidth is ~100 MHz; high analog input
bandwidth is ~200 MHz.
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| AD9981KSTZ-95 | 功能描述:IC INTERFACE 10BIT ANALOG 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9981XSTZ-110 | 制造商:Analog Devices 功能描述:HIGH PERFORMANCE 10-BIT DISPLAY INTERFACE - Bulk |
| AD9983A | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983A/PCBZ | 功能描述:KIT EVALUATION AD9983A RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
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