參數(shù)資料
型號: AD9981
廠商: Analog Devices, Inc.
英文描述: High Performance 10-Bit Display Interface
中文描述: 高性能10位顯示接口
文件頁數(shù): 25/44頁
文件大?。?/td> 506K
代理商: AD9981
AD9981
Rev. 0 | Page 25 of 44
Hexadecimal
Address
Read and
Write or
Read Only
Bits
6
Default
Value
*0** ****
Register Name
Description
Coast Polarity Override.
0 = The chip selects the external Coast polarity.
1 = The polarity of the external Coast signal is set by 0x18, Bit 5.
Coast Input Polarity.
This bit is used only if 0x18, Bit 6 is set to 1.
0 = Active low external Coast.
1 = Active high external Coast.
Clamp Source Select.
0 = Use the internal clamp generated from Hsync.
1 = Use the external clamp signal.
Red Clamp.
0 = Clamp the red channel to ground.
1 = Clamp the red channel to midscale.
Green Clamp.
0 = Clamp the green channel to ground.
1 = Clamp the green channel to midscale.
Blue Clamp.
0 = Clamp the blue channel to ground.
1 = Clamp the blue channel to midscale.
Must be set to 0 for proper operation.
Places the clamp signal an integer of clock periods after the
trailing edge of the Hsync signal.
Number of clock periods that the clamp signal is actively
clamping.
External clamp polarity override.
0 = The chip selects the clamp polarity.
1 = The polarity of the clamp signal is set by 0x1B, Bit 6.
External Clamp Input Polarity. This bit is used only if 0x1B, Bit 7 is
set to 1.
0 = Active low external clamp.
1 = Active high external clamp.
0 = Auto-offset is disabled.
1 = Auto-offset is enabled (offsets become the desired clamp
code).
This selects how often the auto-offset circuit operates. 00 = every
clamp; 01 = 16 clamps; 10 = every 64 clamps; 11 = every Vsync.
Must be written to default (011) for proper operation.
Must be set to 0xFF for proper operation.
SOG slicer threshold. Sets the voltage level of the SOG slicer’s
comparator.
SOGOUT Polarity.
Sets the polarity of the signal on the SOGOUT pin.
0 = Active low SOGOUT.
1 = Active high SOGOUT.
SOGOUT Select.
00 = Raw SOG from sync slicer (SOG0 or SOG1).
01 = Raw Hsync (Hsync0 or Hsync1).
10 = Regenerated sync from sync filter.
11 = Filtered sync from sync filter.
Channel Select Override.
0 = The chip determines which input channels to use.
1 = The input channel selection is determined by 0x1E, Bit 6.
Channel Select.
Input channel select: this is used only if 0x1E, Bit 7 is set to 1, or if
syncs are present on both channels.
0 = Channel 0 syncs and data are selected.
1 = Channel 1 syncs and data are selected.
5
**1* ****
4
***0 ****
3
**** 0***
2
**** *0**
1
**** **0*
0x19
R/W
0
7:0
**** ***0
0000 1000
Clamp
Placement
Clamp Duration
0x1A
R/W
7:0
0010 0000
0x1B
R/W
7
0*** ****
Clamp and
Offset
6
*1** ****
5
**0* ****
4:3
***1 1***
0x1C
0x1D
R/W
R/W
2:0
7:0
7:3
**** *011
1111 1111
0111 1***
TestReg0
SOG Control
2
**** *0**
1:0
**** **00
0x1E
R/W
7
*** ****
Power
6
*0** ****
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參數(shù)描述
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