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參數(shù)資料
| 型號： | AD995PCBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數(shù)字上變頻器w/18-Bit智商數(shù)據(jù)路徑和14位DAC |
| 文件頁數(shù)： | 16/38頁 |
| 文件大?。?/td> | 602K |
| 代理商： | AD995PCBZ |
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AD9957
PRELIMINARY TECHNICAL DATA
Rev. PrF | Page 16 of 38
two outputs. The use of balanced outputs reduces the amount of
common-mode noise at the DAC output, increasing signal-to-
noise ratio. An external resistor (R
SET
) connected between the
DAC_R
SET
pin and the DAC ground (AGND_DAC) establishes
a reference current. The full-scale output current of the DAC
(I
OUT
) is produced as a scaled version of the reference current
(see the Auxiliary DAC section that follows).
Proper attention should be paid to the load termination to keep the
output voltage within the specified compliance range, as voltages
developed beyond this range will cause excessive distortion and
might even damage the DAC output circuitry.
Auxiliary DAC
The full scale output current of the main DAC (I
OUT
) is con-
trolled by an 8-bit auxiliary DAC. An 8-bit code word stored in
the appropriate register map location sets I
OUT
according to the
following equation:
+
=
96
4
86
R
CODE
I
SET
OUT
(6)
Where R
SET
is the value of the R
SET
resistor (in ohms) and CODE
is the 8-bit value supplied to the auxiliary DAC (default is 127).
For example, with R
SET
=10,000 and CODE=127, then
I
OUT
=20.07mA.
INTERPOLATING DAC MODE
A block diagram of the AD9957 operating in the interpolating
DAC mode is shown in Figure 11; grayed out items are inactive.
In this mode, the Q data path, DDS and modulator are all dis-
abled; only the I data path is active.
CCI
(1x -63x)
DDS
cos(
ω
t+
θ
)
sin(
ω
t+
θ
)
DAC
(14-b)
θ
Halfband
Filters
(4x)
18
Parallel Data
Timing &
Control
I/Q In
Internal Clock Timing & Control
PDClk
Clock
Multiplier
RefClk
P
RefClk
Halfband
Filters
(4x)
Inv.
CCI
Inv.
CCI
DAC
Rset
Iout
Iout
1
0
1
D
R
0
1
AD9957: Interpolating DAC Mode
0
3
2
1
0
1
x
sin(x)
TxEn
ω
2
0
1
2
C
OSF
AUX
DAC
(8-b)
8
DAC
Gain
Serial I/O
Port
S
S
Programming
Registers
2
S
P
3
R
RAM
Power
Down
Control
P
D
C
I
Q
C
S
θ
F
2
S
2
G
O
FTW
θ
0
1
Freq.
Ramp
Logic
PW
F
0
1
R
R
CCI
(1x -63x)
Q
I
I
Figure 11: Interpolating DAC Mode
As in the quadrature modulation mode, the PDCLK pin func-
tions as a clock which serves to synchronize the input of data to
the AD9957. The PDCLK rate is given below. Note that it oper-
ates at a rate that is half of that for the quadrature modulation
mode.
R
f
f
SYSCLK
4
DATA
=
(Interpolating DAC mode)
Because no modulation takes place, the spectrum of the data
supplied at the parallel port remains at base band. However, a
sample rate conversion takes place based on the programmed
interpolation rate. The interpolation hardware processes the
signal, by effectively performing an over-sample with zero-
stuffing operation. However, the original input spectrum re-
mains intact and the images that would otherwise occur from
the sample rate conversion process are suppressed by the inter-
polation signal chain.
The PDCLK pin is an output and serves as a data clock timing
source. The output clock rate is f
DATA
as explained in the
Input
Data Assembler
section. Each PDCLK rising edge latches a data
word into the I data path.
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