參數(shù)資料
型號(hào)： AD9958BCPZ-REEL7
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： 2-Channel 500 MSPS DDS with 10-Bit DACs
中文描述： SPECIALTY ANALOG CIRCUIT, QCC56
封裝： 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件頁(yè)數(shù)： 6/40頁(yè)
文件大小： 1051K
代理商： AD9958BCPZ-REEL7
AD9958
Parameter
Residual Phase Noise @ 15.1 MHz (f
OUT
)
w/REF_CLK Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Residual Phase Noise @ 40.1 MHz (f
OUT
)
w/REF_CLK Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Residual Phase Noise @ 75.1 MHz (f
OUT
) w/REF_CLK
Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
Residual Phase Noise @ 100.3 MHz (f
OUT
) w/REF_CLK
Multiplier Enabled 20×
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
SERIAL PORT TIMING CHARACTERISTICS
Maximum Frequency Serial Clock (SCLK)
Minimum SCLK Pulse Width Low (t
PWL
)
Minimum SCLK Pulse Width High (t
PWH
)
Minimum Data Set-Up Time (t
DS
)
Minimum Data Hold Time
Minimum CSB Set-Up Time (t
PRE
)
Minimum Data Valid Time for Read Operation
MISCELLANEOUS TIMING CHARACTERISTICS
Master_Reset Minimum Pulse Width
I/O_Update Minimum Pulse Width
Minimum Set-Up Time (I/O_Update to SYNC_CLK)
Minimum Hold Time (I/O_Update to SYNC_CLK)
Minimum Set-Up Time (Profile Inputs to SYNC_CLK)
Minimum Hold Time (Profile Inputs to SYNC_CLK)
Minimum Set-Up Time (SDIO Inputs to SYNC_CLK)
Minimum Hold Time (SDIO Inputs to SYNC_CLK)
Propagation Time Between REF_CLK and SYNC_CLK
CMOS LOGIC INPUTS
V
IH
V
IL
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load)
V
OH
V
OL
POWER SUPPLY
Total Power Dissipation
—
Both Channels On, Single-
Tone Mode
Total Power Dissipation
—
Both Channels On, with
Sweep Accumulator
Total Power Dissipation
—
Full Power Down
IAVDD
—
Both Channels On, Single Tone Mode
Rev. 0 | Page 6 of 40
Min
Typ
Max
Unit
Test Conditions/Comments
–127
–136
–139
–138
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–117
–128
–132
–130
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–110
–121
–125
–123
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
1.6
2.2
2.2
0
1.0
12
1
1
4.8
0
5.4
0
2.5
0
2.25
2.0
2.7
–107
–119
–121
–119
3.5
3
12
2
315
200
5.5
0.8
12
0.4
380
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
μA
μA
pF
V
V
mW
Min pulse width = 1 sync clock period
Min pulse width = 1 sync clock period
Rising edge to rising edge
Rising edge to rising edge
Dominated by supply variation
350
420
mW
Dominated by supply variation
13
90
105
mW
mA
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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