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參數(shù)資料
| 型號： | AD9958 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 2-Channel 500 MSPS DDS with 10-Bit DACs |
| 中文描述： | 雙通道500 MSPS的DDS的10位DAC |
| 文件頁數(shù)： | 10/40頁 |
| 文件大?。?/td> | 1051K |
| 代理商： | AD9958 |
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AD9958
Pin No.
24
Rev. 0 | Page 10 of 40
Mnemonic
CLK_MODE_SEL
I/O
I
Description
Control Pin for the Oscillator Section. CAUTION: Do not drive this pin beyond 1.8 V.
When high (1.8 V), the oscillator section is enabled to accept a crystal as the
REF_CLK source. When low, the oscillator section is bypassed.
Connects to the external zero compensation network of the PLL loop filter.
Typically the network consists of a 0 resistor in series with a 680 pF capacitor tied
to AVDD.
No Connection.
Data pins used for modulation (FSK, PSK, ASK), start/stop for the sweep
accumulators or are used to ramp up/down the output amplitude. Note the
SYNC_CLK must be enabled in these modes. Any toggle of these data inputs is
equivalent to an I/O_UPDATE. The data is synchronous to the SYNC_CLK (Pin 54).
The data inputs must meet the set-up and hold time requirements to the
SYNC_CLK. This guarantees a fixed pipeline delay of data to the DAC output;
otherwise, a ±1 SYNC_CLK period of uncertainty exists. The functionality of these
pins is controlled by profile pin configuration (PPC) bits in Register FR1 <12:14>.
A rising edge transfers data from the serial I/O port buffer to active registers.
I/O_UPDATE is synchronous to the SYNC_CLK (Pin 54). I/O_UPDATE must meet the
set-up and hold time requirements to the. SYNC_CLK to guarantee a fixed pipeline
delay of data to DAC output. If not, a ±1 SYNC_CLK period of uncertainty exists.
The minimum pulse width is one SYNC_CLK period.
Active low chip select allowing multiple devices to share a common I/O bus (SPI).
Serial Data Clock for I/O Operations. Data bits are written on the rising edge of
SCLK and read on the falling edge of SCLK.
3.3 V Digital Power Supply for SPI Port and Digital I/O.
Data Pin SDIO_0 is dedicated to the Serial Port I/O only.
Data Pins SDIO_1:3 can be used for the serial port I/O port or used to initiate a
ramp up/down (RU/RD) of the DAC output amplitude.
The SYNC_CLK runs at one fourth the system clock rate. It can be disabled.
I/O_UPDATE or data (Pins 40 to 43) is synchronous to the SYNC_CLK. To guarantee
a fixed pipeline delay of data to DAC output, I/O_UPDATE or data (Pins 40 to 43)
must meet the set-up and hold time requirements to the rising edge of SYNC_CLK.
If not, a ±1 SYNC_CLK period of uncertainty exists.
27
LOOP_FILTER
I
28, 32, 34, 38
40, 41,42,43
NC
P0, P1, P2, P3
-
I
46
I/O_UPDATE
I
47
48
CS
SCLK
I
I
49
50
51 52, 53
DVDD_I/O
SDIO_0,
SDIO_1 SDIO_2,
SDIO_3
SYNC_CLK
I
I/O
I/O
54
O
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
| AD9958/PCBZ | 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9958/PCBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD9958 DIRECT DIGITAL SYNTHE |
| AD9958_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel, 500 MSPS DDS with 10-Bit DACs |
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