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參數(shù)資料
| 型號： | AD9957BSVZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 40/60頁 |
| 文件大小： | 840K |
| 代理商： | AD9957BSVZ |
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AD9957
Rev. 0 | Page 40 of 60
LVDS
RECEIVER
PROGAMMABLE
DELAY
5
INTERNAL
CLOCKS
CLOCK
STATE
6
SYNC STATE
PRESET VALUE
SYNC PULSE
SYSCLK
SETUP AND HOLD
VALIDATION
4
D1
D2
Q1
Q2
LOAD
D6
D5
D4
D3
Q6
Q5
Q4
Q3
DELAYED SYNC-IN SIGNAL
SYNC
RECEIVER
DELAY
SYNC
RECEIVER
ENABLE
SYNC_SMP_ERR
SYNC_IN
7
8
12
RISING EDGE
DETECTOR
AND
STROBE
GENERATOR
SYNC
TIMING
VALIDATION
DISABLE
SYNC
VALIDATION
DELAY
0
CLOCK
GENERATOR
Figure 56. Sync Receiver
CLOCK
SOURCE
SYNC
IN
SYNC
OUT
REF_CLK
NUMBER 1
MASTER DEVICE
FPGA
DATA
FPGA
DATA
FPGA
DATA
EDGE
ALIGNED
AT REF_CLK
INPUTS.
EDGE
ALIGNED
AT SYNC_IN
INPUTS.
P
SYNC
IN
SYNC
OUT
REF_CLK
NUMBER 2
P
SYNC
IN
SYNC
OUT
REF_CLK
NUMBER 3
P
(FOR EXAMPLE AD951x)
CLOCK DISTRIBUTION
AND
DELAY EQUALIZATION
SYNCHRONIZATION
DISTRIBUTION AND
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
0
Figure 57. Multichip Synchronization Example
The sync receiver accepts a periodic clock signal at the
SYNC_IN pins. This signal is assumed to originate from an
LVDS-compatible driver. The user can delay the SYNC_IN
signal in steps of ~150 ps by programming the 5-bit sync
receiver delay word in the multichip sync register. For
clarification, the signal at the output of the programmable delay
is referred to as the delayed sync-in signal.
The edge detection logic generates a synchronization pulse
having a duration of one SYSCLK cycle with a repetition rate
equal to the frequency of the signal applied to the SYNC_IN
pins. The sync pulse is generated as a result of sampling the
rising edge of the delayed sync-in signal with the rising edge of
the local SYSCLK. The synchronization pulse is routed to the
internal clock generator, which behaves as a presettable counter
clocked at the SYSCLK rate. The sync pulse presets the counter
to a predefined state (programmable via the 6-bit sync state
preset value word in the multichip sync register). The predefined
state is only active for a single SYSCLK cycle, after which the
clock generator resumes cycling through its state sequence at
the SYSCLK rate. This unique state presetting mechanism gives
the user the flexibility to synchronize devices with specific
relative clock state offsets (by assigning a different sync state
preset value word to each device).
Multiple device synchronization is accomplished by providing
each AD9957 with a SYNC_IN signal that is edge aligned across
all the devices. If the SYNC_IN signal is edge aligned at all devices,
and all devices have the same sync receiver delay and sync state
preset value, then they all have matching clock states (that is,
they are synchronized). This concept is shown in Figure 57 in
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
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