參數(shù)資料
型號： AD9949KCPZRL
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： 12-Bit CCD Signal Processor with Precision Timing Core
中文描述： SPECIALTY CONSUMER CIRCUIT, QCC40
封裝： 6 X 6 MM, LEAD FREE, MO-220-VJJD-2, LFCSP-40
文件頁數(shù)： 7/36頁
文件大?。?/td> 707K
代理商： AD9949KCPZRL
AD9949
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. B | Page 7 of 36
0
AD9949
TOP VIEW
1
D1
D2
2
D8
D7
DRVD5
DRVD4
D3
3
4
5
6
7
8
9
10
R
H
H
H
H
H
H
(
D
D
1
1
1
1
1
1
1
1
2
30
REFB
REFT
29
28
27
26
25
24
23
22
21
RG
RGVDD
TCVDD
AVDD
AVSS
4
3
3
3
3
3
3
3
3
3
D
C
H
D
D
H
V
S
S
PIN 1
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
1 to 4
D1 to D4
5
DRVSS
6
DRVDD
7 to 13
D5 to D11
14
H1
15
H2
16
HVSS
17
HVDD
18
H3
19
H4
20
RGVSS
21
RG
22
RGVDD
23
TCVSS
24
TCVDD
25
CLI
26
AVDD
27
CCDIN
28
AVSS
29
REFT
30
REFB
31
SL
32
SDI
33
SCK
34
VD
35
HD
36
DVSS
37
DVDD
38
HBLK
39
CLP/PBLK
40
D0
Type
1
DO
P
P
DO
DO
DO
P
P
DO
DO
P
DO
P
P
P
DI
P
AI
P
AO
AO
DI
DI
DI
DI
DI
P
P
DI
DO
DO
Description
Data Outputs
Digital Driver Ground
Digital Driver Supply
Data Outputs (D11 is MSB)
CCD Horizontal Clock 1
CCD Horizontal Clock 2
H1 to H4 Driver Ground
H1 to H4 Driver Supply
CCD Horizontal Clock 3
CCD Horizontal Clock 4
RG Driver Ground
CCD Reset Gate Clock
RG Driver Supply
Analog Ground for Timing Core
Analog Supply for Timing Core
Master Clock Input
Analog Supply for AFE
Analog Input for CCD Signal (Connect through Series 0.1 μF Capacitor)
Analog Ground for AFE
Reference Top Decoupling (Decouple with 1.0 μF to AVSS)
Reference Bottom Decoupling (Decouple with 1.0 μF to AVSS)
3-Wire Serial Load
3-Wire Serial Data Input
3-Wire Serial Clock
Vertical Sync Pulse
Horizontal Sync Pulse
Digital Ground
Digital Supply
Optional HBLK Input
CLPOB or PBLK Output
Data Output LSB
1
Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power.
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AD9949KCPRL 12-Bit CCD Signal Processor with Precision Timing Core
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