參數(shù)資料
型號(hào): AD9948KCPRL
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: 10-Bit CCD Signal Processor with Precision Timing⑩ Core
中文描述: SPECIALTY CONSUMER CIRCUIT, QCC40
封裝: 6 X 6 MM, MO-220-VJJD-2, LFCSP-40
文件頁數(shù): 22/28頁
文件大小: 539K
代理商: AD9948KCPRL
REV. 0
–22–
AD9948
2
2
0
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VD
NOTES
1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES.
3. FIELDVAL IS ALWAYS RESET TO 0 ON VD FALLING EDGES.
HD
1
1
0
X
X
PxGA GAIN
REGISTER
FIELDVAL
0
FIELDVAL = 0
0
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0
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3
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1
0
0
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0
FIELDVAL = 0
Figure 18a. PxGA Color Steering—Progressive Mode
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0
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1
1
2
2
VD
NOTES
1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE.
3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER 0 (FIELDVAL = 0) OR 2 (FIELDVAL = 1).
4. FIELDVAL WILL TOGGLE BETWEEN 0 AND 1 ON EACH VD FALLING EDGE.
HD
1
1
0
X
X
PxGA GAIN
REGISTER
FIELDVAL
0
FIELDVAL = 0
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1
1
0
0
0
0
3
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2
1
1
FIELDVAL = 1
FIELDVAL = 0
Figure 18b. PxGA Color Steering—Interlaced Mode
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2
3
3
3
2
2
VD
NOTES
1. FIELDVAL = 0 (START OF FIRST FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
2. FIELDVAL = 1 (START OF SECOND FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 2323 LINE.
2. FIELDVAL = 2 (START OF THIRD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO 0101 LINE.
3. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN 0101 AND 2323 LINES.
4. FIELDVAL WILL INCREMENT AT EACH VD FALLING EDGE, REPEATING THE 0...1...2...0...1...2 PATTERN.
HD
1
1
0
X
X
PxGA GAIN
REGISTER
FIELDVAL
0
FIELDVAL = 0
3
1
1
0
0
2
2
0
0
1
1
3
3
FIELDVAL = 1
FIELDVAL = 2
Figure 18c. PxGA Color Steering—Three-Field Mode
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