參數(shù)資料
型號: AD9945KCPZRL72
廠商: Analog Devices, Inc.
英文描述: Complete 12-Bit 40 MHz CCD Signal Processor
中文描述: 完整的12位40 MHz的CCD信號處理器
文件頁數(shù): 3/16頁
文件大?。?/td> 217K
代理商: AD9945KCPZRL72
REV. A
AD9945
–3–
Parameter
Min
Typ
Max
Unit
Notes
CDS
Maximum Input Range before Saturation
*
Allowable CCD Reset Transient
*
Maximum CCD Black Pixel Amplitude
*
1.0
500
100
Vp-p
mV
mV
See Input Waveform in Footnote
VARIABLE GAIN AMPLIFIER (VGA)
Gain Control Resolution
Gain Monotonicity
Gain Range
Minimum Gain
Maximum Gain
1024
Steps
Guaranteed
5.3
41.5
dB
dB
See Figure 7 for VGA Gain Curve
See Variable Gain Amplifier Section for
VGA Gain Equation
40.0
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Minimum Clamp Level
Maximum Clamp Level
256
Steps
Measured at ADC Output
0
255
LSB
LSB
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Data Output Coding
Full-Scale Input Voltage
12
Bits
LSB
±
0.5
Guaranteed
Straight Binary
2.0
V
VOLTAGE REFERENCE
Reference Top Voltage (REFT)
Reference Bottom Voltage (REFB)
2.0
1.0
V
V
SYSTEM PERFORMANCE
Gain Range
Low Gain (VGA Code = 0)
Maximum Gain (VGA Code = 1023)
Gain Accuracy
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
Specifications Include Entire Signal Chain
5.3
41.5
1.0
0.1
1.2
40
dB
dB
dB
%
LSB rms
dB
40.0
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
*
Input Signal Characteristics defined as follows:
500mV TYP
RESET TRANSIENT
100mV TYP
OPTICAL BLACK PIXEL
1V TYP
INPUT SIGNAL RANGE
Specifications subject to change without notice.
SYSTEM SPECIFICATIONS
(T
MIN
to T
MAX
, AVDD = DVDD = DRVDD = 3.0 V, f
SAMP
= 40 MHz, unless otherwise noted.)
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