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參數(shù)資料
| 型號： | AD9944KCPZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, QCC32 |
| 封裝： | 5 X 5 MM, LEAD FREE, MO-220-VHHD-2, LFCSP-32 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大小： | 485K |
| 代理商： | AD9944KCPZRL |
AD9943/AD9944
INTERNAL REGISTER MAP
All register values default to 0x000 at power-up except clamp level, which defaults to 128 decimal (AD9943 = 32 LSB clamp level, and
AD9944 = 128 LSB clamp level).
Table 9.
Address Bits
Register Name
A2
A1
A0
Data Bits
Function
Operation
0
0
0
D0
Software Reset (0 = normal operation, 1 = reset all registers to default).
D2, D1
Power-Down Modes (00 = normal power, 01 = standby, 10 = total shutdown).
D3
OB Clamp Disable (0 = clamp on, 1 = clamp off).
D5, D4
Test Mode. Should always be set to 00.
D6
PBLK Blanking Level (0 = blank output to zero, 1 = blank to ob clamp level).
D8, D7
Test Mode 1. Should always be set to 00.
D11 to D9
Test Mode 2. Should always be set to 000.
Control
0
0
1
D0
SHP/SHD Input Polarity (0 = active low, 1 = active high).
D1
DATACLK Input Polarity (0 = active low, 1 = active high).
D2
CLPOB Input Polarity (0 = active low, 1 = active high).
D3
PBLK Input Polarity (0 = active low, 1 = active high).
D4
Three-State Data Outputs (0 = outputs active, 1 = outputs three-stated).
D5
Data Output Latching (0 = latched by DATACLK, 1 = latch is transparent).
D6
Data Output Coding (0 = binary output, 1 = gray code output).
D11 to D7
Test Mode. Should always be set to 00000.
Clamp Level
0
1
0
D7 to D0
OB Clamp Level (AD9943: 0 = 0 LSB, 255 = 63.75 LSB,
AD9944: 0 = 0 LSB, 255 = 255 LSB).
VGA Gain
0
1
1
D9 to D0
VGA Gain (0 = 6 dB, 1023 = 40 dB).
Rev. B | Page 13 of 20
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9945KCPRL7 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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