- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373971 > AD9942BBCZRL (ANALOG DEVICES INC) Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core PDF資料下載
參數(shù)資料
| 型號： | AD9942BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA100 |
| 封裝： | 9 X 9 MM, LEAD FREE, MO-205AB, CSPBGA-100 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大?。?/td> | 452K |
| 代理商： | AD9942BBCZRL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁當前第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD9942
CHANNEL A AND CHANNEL B
VARIABLE GAIN AMPLIFIER
The VGA stage provides a gain range of 0 dB to 18 dB, pro-
grammable with 9-bit resolution through the serial digital
interface. A minimum gain of 6 dB is needed to match a 1 V
input signal with the ADC full-scale range of 2 V.
Rev. A | Page 28 of 36
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain can be calculated for any gain register value by
using the equation
Gain
(dB) = (0.035 ×
VGAGAIN
Code
)
where the code range is 0 to 511.
20
0
2
4
6
8
10
12
14
16
18
0
50
100
150
200
250
300
350
400
450
500
0
GAIN CODE (Decimal)
G
Figure 29. VGA Gain Curve
CHANNEL A AND CHANNEL B ADC
The AD9942 uses a high performance ADC architecture, opti-
mized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB. The ADC
uses a 2 V input range. See Figure 8 and Figure 9 for typical
linearity and noise performance plots for the AD9942.
CHANNEL A AND CHANNEL B CLPOB
The CLPOB loop is used to remove residual offsets in the signal
chain and to track low frequency variations in the CCD black
level. During the optical black (OB), or shielded, pixel interval
on each line, the ADC output is compared with a fixed black
level reference, selected by the user in the CLAMP LEVEL
register. The value can be programmed between 0 LSB and 255
LSB in 256 steps. The resulting error signal is filtered to reduce
noise, and the correction value is applied to the ADC input
through a digital-to-analog converter. Typically, the CLPOB
loop is turned on once per horizontal line, but this loop can be
updated more slowly to suit a particular application. If external
digital clamping is used during postprocessing, the AD9942
CLPOB can be disabled using Bit D2 in the OPRMODE register.
The CLAMP LEVEL register can be used to provide program-
mable offset adjustment even when the loop is disabled.
The CLPOB pulse should be placed during the CCD’s OB pixel
region. It is recommended that the CLPOB pulse duration be at
least 20 pixels wide to minimize clamp noise. Shorter pulse widths
can be used, but clamp noise might increase and the ability to
track low frequency variations in the black level is reduced. See
the Channel A and Channel B Horizontal Clamping and
Blanking section and the Applications Information section for
timing examples.
CHANNEL A AND CHANNEL B
DIGITAL DATA OUTPUTS
The AD9942 digital output data is latched using the
DOUTPHASE register value, as shown in Figure 28. (Output
data timing is shown in Figure 19 and Figure 20.) It is also possible
to leave the output latches transparent, so that the data outputs
are valid immediately from the ADC. Programming the AFE
Control Register Bit D4 to 1 sets the output latches transparent.
The data outputs can also be disabled (three-stated) by setting
the AFE Control Register Bit D3 to 1.
The data output coding is typically straight binary, but the
coding can be changed to gray coding by setting the AFE
Control Register Bit D5 to 1.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9943 | Label Printer Tape RoHS Compliant: NA |
| AD9944 | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCPZRL | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9944KCP | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9944KCPRL | Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9943 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
| AD9943KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:10 BIT 25 MHZ LOW COST ANALOG FRONT END - Bulk |
| AD9943KCPRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 10-Bit 3V 32-Pin LFCSP EP T/R |
| AD9943KCPZ | 功能描述:IC CCD SIGNAL PROCESSOR 32-LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 傳感器和探測器接口 系列:- 其它有關(guān)文件:Automotive Product Guide 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:74 系列:- 類型:觸控式傳感器 輸入類型:數(shù)字 輸出類型:數(shù)字 接口:JTAG，串行 電流 - 電源:100µA 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:20-TSSOP 包裝:管件 |
| AD9943KCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Complete 10-Bit and 12-Bit, 25 MHz CCD Signal Processors |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。