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參數(shù)資料
| 型號： | AD9923A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with V-Driver and Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器與V - Driver和精確定時⑩發(fā)生器 |
| 文件頁數(shù)： | 55/88頁 |
| 文件大?。?/td> | 852K |
| 代理商： | AD9923A |
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AD9923A
FG_TRIG OPERATION
The AD9923A contains one additional signal that can be used
in conjunction with shutter operation or general system
operation. The FG_TRIG signal is an internally generated pulse
that can be output on the SYNC pins for shutter or other system
functions. A unique feature of the FG_TRIG signal is that it is
output with respect to the MODE register field status.
Rev. 0 | Page 55 of 88
The FG_TRIG signal is generated using the SHUT1 start
polarity and toggle position registers, programmable with line
and pixel resolution. The field registers for SHUT1 are ignored
because the field placement of the FG_TRIG pulse is matched
to the field count specified by the MODE register operation.
The FG_TRIGEN register contains a three-bit value that specifies
which field count contains the FG_TRIG pulse. Figure 72 shows
how the FG_TRIG pulse is generated using these registers.
After the FG_TRIG signal is specified, it can be enabled using
Bit 3 of the FG_TRIGEN register. The FG_TRIG signal is
mapped to the SYNC output if the SYNC pin is configured as
an output (SYNCENABLE = 0).
Table 40. FG_TRIG Operation Registers
Register
SYNCENABLE
FG_TRIGEN
SHUT1POL
SHUT1_ON_LN
SHUT1_ON_PX
SHUT1_OFF_LN 0x76
SHUT1_OFF_PX
Address
0x12
0xF1
0x72
0x74
0x74
Bit Location
[0]
[3:0]
[1]
[11:0]
[25:13]
[11:0]
[25:13]
Description
0 = configures SYNC pin as an output. By default, the FG_TRIG signal is output on the SYNC pin.
1 = SYNC pin is an external synchronization input.
[2:0] selects the field count for the pulse based on the mode field counter.
[3] = 1 to enable FG_TRIG signal output.
[1] FG_TRIG start polarity.
FG_TRIG first toggle, line location.
FG_TRIG first toggle, pixel location.
FG_TRIG second toggle, line location.
FG_TRIG second toggle, pixel location.
0x76
VD
FG_TRIG PROGRAMMABLE SETTINGS:
1
ACTIVE POLARITY.
2
FIRST TOGGLE POSITION, LINE AND PIXEL LOCATION.
3
SECOND TOGGLE POSITION, LINE AND PIXEL LOCATION.
4
FIELD PLACEMENT BASED ON MODE REGISTER FIELD COUNT.
MODE REGISTER
FIELD COUNT
FG_TRIG
1
2
3
FIELD 0
FIELD 1
FIELD 2
FIELD 0
FIELD 1
4
4
0
Figure 72. FG_TRIG Signal Generation
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