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參數(shù)資料
| 型號： | AD9911BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 33/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DDS 500MSPS DAC 10BIT 56LFCSP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 750 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 500MHz |
| 調節(jié)字寬（位）： | 32 b |
| 電源電壓： | 1.71 V ~ 1.96 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 56-LFCSP-VQ（8x8） |
| 包裝： | 帶卷 (TR) |
| 配用： | AD9911/PCBZ-ND - BOARD EVAL FOR AD9911 |
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AD9911
Rev. 0 | Page 39 of 44
FR1 <12:14> profile pin configuration bits.
The profile pin configuration bits assign the profile and SDIO
pins for the different tasks. See the Shift Keying Modulation
section for examples.
FR1 <15> inactive.
FR1 <17:16> charge pump current control.
FR1 <17:16> = 00 (default), the charge pump current is 75 μA.
= 01 charge pump current is 100 μA.
= 10 charge pump current is 125 μA.
= 11 charge pump current is 150 μA.
FR1 <22:18> PLL divider values.
FR1 <22:18>, if the value is > 3 and < 21, the PLL is enabled and
the value sets the multiplication factor. If the value is < 4 or >20
the PLL is disabled.
FR1 <23> PLL VCO gain.
FR1 <23> = 0 (default), the low range (system clock below
160 MHz). FR1 <23> = 1, the high range (system clock above
255 MHz).
Function Register 2 (FR2) Description
The FR2 is comprised of two bytes located in Address 0x02.
The FR2 is used to control the various functions, features, and
modes of the AD9911. The functionality of each bit is as
follows:
FR2<1:0> system clock offset. See the Synchronizing Multiple
AD9911 Devices section for more details.
FR2 <3:2> inactive.
FR2 <4:7>. Multidevice synchronization bits. See the
Synchronizing Multiple AD9911 Devices section for more
details.
FR2 <11:8> inactive.
FR2 <12> Clear phase accumulator.
FR2 <12> = 0 (default), the phase accumulator functions as
normal. FR2 <12> = 1, the phase accumulator memory
elements are asynchronously cleared.
FR2 <13> Auto clear phase accumulator.
FR2 <13> = 0 (default). A new frequency tuning word is applied
to the inputs of the phase accumulator, but not loaded into the
accumulator.
FR2 <13> = 1. This bit automatically synchronously clears
(loads zeros into) the phase accumulator for one cycle upon
reception of the I/O update sequence indicator on both
channels.
FR2 <14> Clear sweep accumulator.
FR2 <14> = 0 (default), the sweep accumulator functions as
normal. FR2 <14> = 1, the sweep accumulator memory
elements are asynchronously cleared.
FR2 <15> Auto clear sweep accumulator.
FR2 <15> = 0 (default). A new delta word is applied to the
input, as in normal operation, but not loaded into the accumu-
lator. FR2 <15> = 1. This bit automatically synchronously clears
(loads 0s) the sweep accumulator for one cycle upon reception
of the I/O_UPDATE sequence indicator on both channels.
CHANNEL FUNCTION REGISTER (CFR)
DESCRIPTION
CFR <0> Enable sine function.
CFR <0> = 0 (default). The angle-to-amplitude conversion logic
employs a cosine function. CFR <0> = 1. The angle-to-
amplitude conversion logic employs a sine function.
CFR <1> Clear phase accumulator.
CFR <1> = 0 (default). The phase accumulator functions as
normal. CFR <1> = 1. The phase accumulator memory
elements are asynchronously cleared.
CFR <2> auto clear phase accumulator.
CFR <2> = 0 (default). A new frequency tuning word is applied
to the inputs of the phase accumulator, but not loaded into the
accumulator. CFR <2> = 1. This bit automatically synchro-
nously clears (loads 0s) the phase accumulator for one cycle
upon reception of the I/O_UPDATE sequence indicator.
CFR <3> clear sweep accumulator.
CFR <3> = 0 (default). The sweep accumulator functions as
normal. CFR <3> = 1. The sweep accumulator memory
elements are asynchronously cleared.
CFR <4> auto clear sweep accumulator.
CFR <4> = 0 (default). A new delta word is applied to the input,
as in normal operation, but not loaded into the accumulator.
CFR <4> = 1. This bit automatically synchronously clears (loads
0s) the sweep accumulator for one cycle upon reception of the
I/O_UPDATE sequence indicator.
CFR <5> match pipe delays active.
CFR <5> = 0 (default), match pipe delay mode is inactive.
CFR <5> = 1, match pipe delay mode is active. See the Single-
Tone Mode—Matched Pipeline Delay section for details.
CFR <6> DAC power-down.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9912 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer w/ 14-bit DAC |
| AD9912/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 1 GSPS Direct Digital Synthesizer W/ 14-Bit DAC 制造商:Analog Devices 功能描述:EVAL KIT FOR 1 GSPS DIRECT DGTL SYNTHESIZER W/ 14BIT DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD AD9912 1GSPS DDS |
| AD9912A/PCBZ | 功能描述:BOARD EVALUATION FOR AD9912 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| AD9912ABCPZ | 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9912ABCPZ-REEL7 | 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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