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參數(shù)資料
| 型號： | AD9889BBBCZ-80 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | TRANSMITTER HDMI/DVI 76-CSPBGA |
| 標準包裝： | 1 |
| 類型： | HDMI，DVI 發(fā)射器 |
| 應(yīng)用： | 錄音機，機頂盒 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
| 配用： | AD9889B/PCBZ-ND - KIT EVALUATION FOR AD9889B |
AD9889B
Rev. A | Page 8 of 12
Pin No.
Mnemonic
Description
BGA
LFCSP
LQFP
K7, K8
27, 28
34, 35
Tx1/Tx1+
O
Differential Output Channel 1. Differential output of the
green data at 10× the pixel clock rate; supports TMDS logic level.
K4, K5
24, 25
30, 31
Tx0/Tx0+
O
Differential Output Channel 0. Differential output of the blue
data at 10× the pixel clock rate; TMDS logic level.
H10
32
40
INT
O
Interrupt. Open drain. A 2 kΩ pull-up resistor to the
microcontroller I/O supply is recommended.
J2, J5, J8, K9
19, 23, 29
24, 29, 36, 41
AVDD
P
1.8 V Power Supply for TMDS Outputs.
D5, D6, D7, E7
1, 48, 49
1, 61, 62, 63, 64
DVDD
P
1.8 V Power Supply for Digital and I/O Power Supply. These
pins supply power to the digital logic and I/Os. They should
be filtered and as quiet as possible.
G4, G5, J1
15, 16, 17,
16, 19, 20, 21
PVDD
P
1.8 V PLL Power Supply. The most sensitive portion of the
AD9889B is the clock generation circuitry. These pins provide
power to the clock PLL. The designer should provide quiet,
noise-free power to these pins.
D4, E4, F4, J4,
G6, J6, K6, F7,
G7, H9, J9
N/A
15, 17, 18, 22,
26, 32, 39, 42,
43, 59, 60, 79, 80
GND
P
Ground. The ground return for all circuitry on-chip. For best
practice, assemble the AD9889B on a single, solid ground
plane with careful attention given to ground current paths.
N/A
64, paddle
on bottom
side
N/A
DGND
P
Digital Ground. The ground return for all circuitry on-chip.
For best practice, assemble the AD9889B on a single, solid
ground plane with careful attention given to ground
current paths.
F9
36
47
SDA
C3
Serial Port Data I/O. This pin serves as the serial port data I/O
slave for register access. Supports CMOS logic levels from
1.8 V to 3.3 V.
F10
35
46
SCL
Serial Port Data Clock. This pin serves as the serial port data
clock slave for register access. Supports CMOS logic levels
from 1.8 V to 3.3 V.
E10
37
48
MDA
Serial Port Data I/O Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
E9
38
49
MCL
Serial Port Data Clock Master to HDCP Key EEPROM. Supports
CMOS logic levels from 1.8 V to 3.3 V.
G9
34
45
DDCSDA
Serial Port Data I/O to Receiver. This pin serves as the master
to the DDC bus. Supports a 5 V CMOS logic level.
G10
33
44
DDCSCL
Serial Port Data Clock to Receiver. This pin serves as the
master clock for the DDC bus. Supports a 5 V CMOS logic level.
1 I = input, O = output, P = power supply, C = control.
2 Pin J7 (BGA), Pin 26 (LFCSP), and Pin 33 (LQFP) are dual function pins: I2C selection and power-down control. The I2C selection function occurs at power-up; the power-
down control function occurs whenever the state of the pin is changed from its original state at power-up.
3 For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from ATV_VideoTx_Apps@analog.com.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9889BBBCZRL-165 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance HDMI/DVI Transmitter |
| AD9889BBBCZRL-80 | 功能描述:TRANSMITTER HDMI/DVI 76-CSPBGA RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD9889BBBSTZ-80 | 制造商:Analog Devices 功能描述:PB-FREE HDMI TX @ 80 MHZ - Trays |
| AD9889BBCPZ-165 | 功能描述:XMITTER HDMI/DVI 165MHZ 64-LFCSP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 標準包裝:250 系列:- 類型:電平移位器 應(yīng)用:LCD 電視機/監(jiān)控器 安裝類型:表面貼裝 封裝/外殼:28-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:28-WQFN（4x4）裸露焊盤 包裝:帶卷 (TR) 其它名稱:296-32523-2TPS65198RUYT-ND |
| AD9889BBCPZ-165 | 制造商:Analog Devices 功能描述:TRANSMITTER, DVI/HDMI, 1.8V, LFCSP-64 |
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