參數(shù)資料
型號(hào): AD9882KST-140
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: Dual Interface for Flat Panel Displays
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝: PLASTIC, MS-026BED, LQFP-100
文件頁(yè)數(shù): 24/36頁(yè)
文件大小: 370K
代理商: AD9882KST-140
REV. A
–24–
AD9882
Table IX. Control Register Map (continued)
Hex
Address
Read and Write
or Read Only
Default
Value
Bit
Register Name
Function
14
R/W
0
****
***
0
Enable 4:2:2
0 = 4:4:4 mode
1 = 4:2:2 mode
0 = Hsync not detected
1 = Hsync detected
0 = Sync signal not detected on green channel
1 = Sync signal detected on green channel
0 = Vsync not detected
1 = Vsync detected
0 = Digital interface clock not detected
1 = Digital interface clock detected
0 = Analog interface active
1 = DVI interface active
0 = Hsync from the Hsync input pin
1 = Hsync from the SOG input
0 = Active low polarity detected
1 = Active high polarity detected
0 = Vsync from the Vsync input pin
1 = Vsync from SOG
0 = Active high polarity detected
1 = Active low polarity detected
0 = Active low polarity detected
1 = Active high polarity detected
This function works only with internal coast.
0 = Not detected
1 = Detected
Must be set to 1000 0000 for proper operation.
Must be set to 1100 000x for proper operation.
Must be set to 0111 110x for proper operation.
Must be set to default for proper operation.
0 = MDA and MCL three-stated
1 = MDA and MCL not three-stated
Must be set to
*
110 0111 for proper operation.
Must be set to default for proper operation.
Reserved for future use.
Reserved for future use.
15
RO
7
Analog Hsync Active
6
Analog SOG Active
5
Analog Vsync Active
4
DVI Active
3
Active Interface
16
RO
7
Active Hsync
6
Hsync Polarity Detected
5
Active Vsync
4
Vsync Polarity Detected
3
Coast Polarity Detected
2
HDCP Keys Detected
17
18
19
1A
1B
R/W
R/W
R/W
R/W
R/W
7
0
7
0
7
0
7
0
7
0000 0000
0000 000X
0000 010X
0011 1111
1
*** ****
Test Register
Test Register
Test Register
Test Register
MDA and MCL
6
0
7
0
7
0
7
0
*
111
0000
0000 1111
Test Register
Test Register
Test Register
Test Register
1C
1D
1E
R/W
RO
RO
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