參數(shù)資料
型號: AD9882
廠商: Analog Devices, Inc.
英文描述: Dual Interface for Flat Panel Displays
中文描述: 雙接口的平板顯示器
文件頁數(shù): 19/36頁
文件大小: 370K
代理商: AD9882
REV. A
AD9882
–19–
Table VIII. Digital Interface Pin List
Pin Type
Mnemonic
Function
Value
Pin Number
Digital Video
Data Inputs
R
X0+
R
X0
R
X1+
R
X1
R
X2+
R
X2
R
XC+
R
XC
R
TERM
Digital Input Channel 0 True
Digital Input Channel 0 Complement
Digital Input Channel 1 True
Digital Input Channel 1 Complement
Digital Input Channel 2 True
Digital Input Channel 2 Complement
33
32
36
35
39
38
Digital Video
Clock Inputs
Digital Data Clock True
Digital Data Clock Complement
41
42
Termination
Control
Control Pin for Setting the Internal Termination
Resistance
28
Outputs
DE
HSOUT
VSOUT
CTL0, CTL1,
CTL2, CTL3
Data Enable
Hsync Output
Vsync Output
Decoded Control Bit Outputs
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
86
88
87
22
25
HDCP
DDCSCL
DDCSDA
MCL
MDA
HDCP Slave Serial Port Data Clock
HDCP Slave Serial Port Data I/O
HDCP Master Serial Port Data Clock
HDCP Master Serial Port Data I/O
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
53
54
81
82
Power Supply
V
D
PV
D
V
DD
GND
Main Power Supply
PLL Power Supply
Output Power Supply
Ground Supply
3.15 V to 3.45 V
3.15 V to 3.45 V
2.2 V to 3.6 V
0 V
DIGITAL INTERFACE PIN DESCRIPTIONS
DIGITAL DATA INPUTS
R
X0+
Positive Differential Input Data (Channel 0)
R
X0
Negative Differential Input Data (Channel 0)
R
X1+
Positive Differential Input Data (Channel 1)
R
X1
Negative Differential Input Data (Channel 1)
R
X2+
Positive Differential Input Data (Channel 2)
R
X2
Negative Differential Input Data (Channel 2)
These six pins receive three pairs of differential, low voltage swing input pixel
data from a DVI transmitter.
DIGITAL CLOCK INPUTS
R
XC+
R
XC
These two pins receive the differential, low voltage swing input pixel clock from
a DVI transmitter.
Positive Differential Input Clock
Negative Differential Input Clock
TERMINATION CONTROL
R
TERM
Internal Termination Set Pin
This pin is used to set the termination resistance
for all of the digital interface high speed inputs.
To set, place a resistor of value equal to 10
the
desired input termination resistance between this
pin (Pin 28) and ground supply. Typically, the
value of this resistor should be 500
W
.
OUTPUTS
DE
Data Enable Output
This pin outputs the state of data enable (DE).
The AD9882 decodes DE from the incoming
stream of data. The DE signal will be HIGH
during active video and will be LOW while there
is no active video.
HDCP Slave Serial Port Data Clock
For use in communicating with the HDCP
enabled DVI transmitter.
HDCP Slave Serial Port I/O
For use in communicating with the HDCP
enabled DVI transmitter.
HDCP Master Serial Port Data Clock
Connects to the EEPROM for reading the
encrypted HDCP keys.
HDCP Master Serial Port Data I/O
Connects to the EEPROM for reading the
encrypted HDCP keys.
Digital Control Outputs
These pins output the control signals for the
Red and Green channels. CTL0 and CTL1
correspond to the Red channel
s input, while
CTL2 and CTL3 correspond to the Green
channel
s input.
DDCSCL
DDCSDA
MCL
MDA
CTL
相關(guān)PDF資料
PDF描述
AD9883ABST-RL140 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
AD9883AKST-110 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
AD9883AKST-140 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
AD9883A 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
AD9883ABST-RL110 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
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