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參數(shù)資料
| 型號： | AD9876-EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 模擬前端 |
| 英文描述： | Broadband Modem Mixed-Signal Front End |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號前端 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 666K |
| 代理商： | AD9876-EB |
REV. A
AD9876
–20–
the first address to be accessed. The AD9876 will automatically
increment the address for each successive byte required for the
multibyte communication cycle.
Figures 10a and 10b show how the serial port words are built
for each of these modes.
SENABLE
SCLK
SDATA
R/WI6
(N)
I5
(N)
I3
I4
I2
I1
I0
D7
N
D6
N
D2
0
D1
0
D0
0
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
Figure 10a. Serial Register Interface Timing MSB-First
SENABLE
SCLK
SDATA
I0
I6
(N)
I5
(N)
I3
I4
I2
I1
R/W
D7
N
D6
N
D2
0
D1
0
D0
0
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
Figure 10b. Serial Register Interface Timing LSB-First
Notes on Serial Port Operation
The serial port is disabled and all registers are set to their default
values during a hardware reset. During a software reset, all
registers except Register 0 are set to their default values. Regis-
ter 0 will remain at the last value sent, with the exception that
the Software Reset Bit will be set to 0.
The serial port is operated by an internal state machine and is
dependent on the number of SCLK cycles since the last time
SENABLE
went active. On every eighth rising edge of SCLK, a
byte is transferred over the SPI. During a multibyte write cycle,
this means the registers of the AD9876 are not simultaneously
updated but occur sequentially. For this reason, it is recom-
mended that single byte transfers be used when changing the
SPI configuration or performing a software reset.
Table IV. Register Layout
Address
(hex)
Default
(hex)
0
×
00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Comments
0
SPI
LSB First
Software
Reset
Read/Write
1
Power-
Down
Regulator
Power-
Down
PLL-B
Power-
Down
PLL-A
Power-
Down
DAC
Power-
Down
Interpolator
Power-
Down
Rx
Reference
Power-
Down
ADC and
FPGA
Power-
Down
Rx LPF and
CPGA
0
×
00
Read/Write
PWR DN
Pin Low
2
Power-
Down
Regulator
Power-
Down
PLL-B
Power-
Down
PLL-A
Power-
Down
DAC
Power-
Down
Interpolator
Power-
Down
Rx
Reference
Power-
Down
ADC and
FPGA
Power-
Down
Rx LPF and
CPGA
0
×
9F
Read/Write
PWR DN
Pin High
3
Tx Port
Negative
Edge
Sampling
ADC Clock
Source
PLL-B/2
PLL-B
(
×
M) Multiplier
<5:4>
PLL-B
( N) Divider
<3:3>
PLL-A
(
×
M) Multiplier
<1:0>
0
×
02
Read/Write
4
Rx Port
Negative
Edge
Sampling
Rx LPF
Tuning
In Progress
(Read-Only)
Rx Path
DC Offset
Correction Bypass
Rx Digital Fast ADC
HPF
Wideband
Rx LPF
Enable
1-Pole
Rx LPF
Rx LPF
Bypass
0
×
01
Read/Write
Sampling
5
Rx LPF f
c
Adjust <7:0>
0
×
80
0
×
00
Read/Write
6
PGA
Gain Set
by Register
Rx Path Gain Adjust <4:0>
Read/Write
7
Interpolation Filter Select
<3:0>
Power-Down
Interpolator
at
Tx QUIET
Pin Low
Tx Port
LS Nibble
First
Tx Port
Demultiplexer
Bypass
0
×
00
Read/Write
8
Invert
CLK-B
Invert
CLK-A
Disable
CLK-B
Disable
CLK-A
Three-State
Rx Port
Rx Port
LS Nibble
First
Rx Port
Multiplexer
Bypass
0
×
00
Read/Write
F
Die Revision Number <3:0>
Read- Only
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