參數(shù)資料
型號(hào)： AD9866
廠商： Analog Devices, Inc.
英文描述： Broadband Modem Mixed Signal Front End
中文描述： 寬帶調(diào)制解調(diào)器混合信號(hào)前端
文件頁(yè)數(shù)： 2/48頁(yè)
文件大?。?/td> 1647K
代理商： AD9866
AD9866
Rev. 0 | Page 2 of 48
TABLE OF CONTENTS
Specifications.....................................................................................3
Tx Path Specifications..................................................................3
Rx Path Specifications..................................................................4
Power Supply Specifications.......................................................5
Digital Specifications...................................................................6
Serial Port Timing Specifications...............................................7
Half-Duplex Data Interface (ADIO Port) Timing
Specifications................................................................................7
Full-Duplex Data Interface (Tx and Rx PORT) Timing
Specifications................................................................................8
Absolute Maximum Ratings............................................................9
Thermal Characteristics..............................................................9
ESD Caution..................................................................................9
Pin Configuration and Function Descriptions...........................10
Typical Performance Characteristics...........................................12
Rx Path Typical Performance Characteristics........................12
TxDAC Path Typical Performance Characteristics...............16
IAMP Path Typical Performance Characteristics..................18
Serial Port ........................................................................................19
Register Map Description .........................................................21
Serial Port Interface (SPI) .........................................................21
Digital Interface..............................................................................23
Half-Duplex Mode.....................................................................23
Full-Duplex Mode......................................................................24
RxPGA Control..........................................................................25
TxPGA Control..........................................................................27
Transmit Path..................................................................................28
Digital Interpolation Filters......................................................28
TxDAC and IAMP Architecture...............................................28
Tx Programmable Gain Control.............................................. 30
TxDAC Output Operation........................................................ 30
IAMP Current Mode Operation.............................................. 30
IAMP Voltage Mode Operation............................................... 31
IAMP Current Consumption Considerations........................ 32
Receive Path.................................................................................... 33
Rx Programmable Gain Amplifier........................................... 33
Low-Pass Filter ........................................................................... 34
Analog to Digital Converter (ADC)........................................ 35
AGC Timing Considerations.................................................... 36
Clock Synthesizer........................................................................... 37
Power Control and Dissipation.................................................... 39
Power-Down............................................................................... 39
Half-Duplex Power Savings...................................................... 39
Power Reduction Options......................................................... 40
Power Dissipation...................................................................... 42
Mode Select upon Power-Up and Reset.................................. 42
Analog and Digital Loop-back Test Modes............................ 43
PCB Design Considerations.......................................................... 44
Component Placement.............................................................. 44
Power Planes and Decoupling.................................................. 44
Ground Planes............................................................................ 44
Signal Routing ............................................................................ 44
Evaluation Board............................................................................ 46
Outline Dimensions....................................................................... 47
Ordering Guide.......................................................................... 47
REVISION HISTORY
Revision 0: Initial Version
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參數(shù)描述
AD9866BCP 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP 制造商:Analog Devices 功能描述:12BIT MIXED SIGNAL CONVERTER 9866
AD9866BCPRL 制造商:Analog Devices 功能描述:Mixed Signal Front End 64-Pin LFCSP EP T/R
AD9866BCPZ 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤
AD9866BCPZRL 功能描述:IC PROCESSOR FRONT END 64LFCSP RoHS:是 類別:RF/IF 和 RFID >> RF 前端 (LNA + PA) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:250 系列:- RF 型:GPS 頻率:1575.42MHz 特點(diǎn):- 封裝/外殼:48-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:48-TQFP 裸露焊盤（7x7） 包裝:托盤
AD9866CHIPS 制造商:AD 制造商全稱:Analog Devices 功能描述:Broadband Modem Mixed Signal Front End
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