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參數(shù)資料
| 型號： | AD9866-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Broadband Modem Mixed Signal Front End |
| 中文描述： | 寬帶調(diào)制解調(diào)器混合信號前端 |
| 文件頁數(shù)： | 38/48頁 |
| 文件大?。?/td> | 1647K |
| 代理商： | AD9866-EB |
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AD9866
CLKOUT1 is a divided version of the VCO output and can be
set to be a submultiple integer of f
DAC
(f
DAC
/2
R
, where R = 0, 1, 2,
or 3). Because this clock is actually derived from the same set of
dividers used within the PLL core, it is phase-locked to them
such that its phase relationship relative to the signal appearing
at OSCIN (or RXCLK)can be determined upon power-up. Also,
this clock has near 50% duty cycle, because it is derived from
the VCO. As a result, CLKOUT1 should be selected before
CLKOUT2 as the primary source for system clock distribution.
Rev. 0 | Page 38 of 48
CLKOUT2 is a divided version of the reference frequency, f
OSCIN
,
and can be set to be a submultiple integer of f
OSCIN
(f
OSCIN
/2
L
,
where L = 0, 1, or 2). With L set to 0, the output of CLKOUT2 is
a delayed version of the signal appearing at OSCIN, exhibiting
the same duty cycle characteristics. With L set to 1 or 2, the
output of CLKOUT2 is a divided version of the OSCIN signal,
exhibiting a near 50% duty cycle, but without having a
deterministic phase relationship relative to CLKOUT1 (or
RXCLK).
Table 22. SPI Registers for CLK Synthesizer
Address (Hex)
Bit
0x04
(4)
(3:2)
(1:0)
0x06
(7:6)
(5)
(4)
(3:2)
(1)
(0)
Description
ADC CLK from PLL
PLL divide factor ( P)
PLL multiplication factor (M )
CLKOUT2 divide number
CLKOUT2 invert
CLKOUT2 disable
CLKOUT1 divide number
CLKOUT1 invert
CLKOUT1 disable
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