參數(shù)資料
型號(hào)： AD9864
廠(chǎng)商： Analog Devices, Inc.
英文描述： IF Digitizing Subsystem
中文描述： 中頻數(shù)字化子系統(tǒng)
文件頁(yè)數(shù)： 4/44頁(yè)
文件大?。?/td> 1984K
代理商： AD9864
AD9864
AD9864 SPECIFICATIONS
Table 1. VDDI = VDDF = VDDA = VDDC = VDDL = VDDH = 2.7 V to 3.6 V, VDDQ = VDDP = 2.7 V to 5.5 V, f
CLK
= 18 MSPS,
f
IF
= 109.65 MHz, f
LO
= 107.4 MHz, f
REF
= 16.8 MHz, unless otherwise noted. Standard operating mode: VGA at minimum attenuation
setting, synthesizers in normal (not fast acquire) mode, decimation factor = 900, 16-bit digital output, and 10 pF load on SSI output pins.
Parameter
Temperature
SYSTEM DYNAMIC PERFORMANCE
1
SSB Noise Figure @ Minimum VGA Attenuation
2, 3
Full
@ Maximum VGA Attenuation
2,3
Full
Dynamic Range with AGC Enabled
2,3
Full
IF Input Clip Point @ Maximum VGA Attenuation
3
Full
@ Minimum VGA Attenuation
3
Full
Input Third Order Intercept (IIP3)
Full
Gain Variation over Temperature
Full
LNA + MIXER
Maximum RF and LO Frequency Range
Full
LNA Input Impedance
25°C
Mixer LO Input Resistance
25°C
LO SYNTHESIZER
LO Input Frequency
Full
LO Input Amplitude
Full
FREF Frequency (for Sinusoidal Input Only)
Full
FREF Input Amplitude
Full
FREF Slew Rate
Full
Minimum Charge Pump Current @ 5 V
4
Full
Maximum Charge Pump Current @ 5 V
4
Full
Charge Pump Output Compliance
5
Full
Synthesizer Resolution
Full
CLOCK SYNTHESIZER
CLK Input Frequency
Full
CLK Input Amplitude
Full
Minimum Charge Pump Output Current
4
Full
Maximum Charge Pump Output Current
4
Full
Charge Pump Output Compliance
5
Full
Synthesizer Resolution
Full
Σ- ADC
Resolution
Full
Clock Frequency (f
CLK
)
Full
Center Frequency
Full
Pass-Band Gain Variation
Full
Alias Attenuation
Full
GAIN CONTROL
Programmable Gain Step
Full
AGC Gain Range
Full
GCP Output Resistance
Full
Rev. 0 | Page 4 of 44
Test Level
IV
IV
IV
IV
IV
IV
IV
IV
V
V
IV
IV
IV
IV
IV
VI
VI
VI
IV
IV
IV
VI
VI
VI
VI
IV
IV
V
IV
IV
V
V
IV
Min
91
–20
–32
–12
300
7.75
0.3
8
0.3
7.5
0.4
6.25
13
0.3
0.4
2.2
16
13
80
50
Typ
7.5
13
95
–19
–31
–7.0
0.7
500
370||1.4
1
0.67
5.3
0.67
5.3
f
CLK
/8
16
12
72.5
Max
9.5
2
300
2.0
25
3
VDDP – 0.4
26
VDDC
VDDQ – 0.4
24
26
1.0
95
Unit
dB
dB
dB
dBm
dBm
dBm
dB
MHz
||pF
k
MHz
V p-p
MHz
V p-p
V/μs
mA
mA
V
kHz
MHz
V p-p
mA
mA
V
kHz
Bits
MHz
MHz
dB
dB
dB
dB
k
1
This includes 0.9 dB loss of matching network.
2
AGC with DVGA enabled.
3
Measured in 10 kHz bandwidth.
4
Programmable in 0.67 mA steps.
5
Voltage span in which LO (or CLK) charge pump output current is maintained within 5% of nominal value of VDDP/2 (or VDDQ/2).
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AD9864-EB IF Digitizing Subsystem
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AD9864-EB 制造商:Analog Devices 功能描述:
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