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參數(shù)資料
| 型號(hào)： | AD9859YSV-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | 400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | EXPOSED PAD, PLASTIC, MS-026ABC, QFP-48 |
| 文件頁數(shù)： | 7/24頁 |
| 文件大?。?/td> | 574K |
| 代理商： | AD9859YSV-REEL7 |
AD9859
PIN FUNCTION DESCRIPTIONS
Table 3. Pin Function Descriptions—48-Lead TQFP/EP
Pin No.
Mnemonic
1
I/O UPDATE
Rev. 0 | Page 7 of 24
I/O
I
Description
The rising edge transfers the contents of the internal buffer memory to the I/O registers. This
pin must be set up and held around the SYNC_CLK output signal.
Digital Power Supply Pins (1.8 V).
Digital Power Ground Pins.
Analog Power Supply Pins (1.8 V).
2, 34
3, 33, 42, 47, 48
4, 6, 13, 16, 18,
19, 25, 27, 29
5, 7, 14, 15, 17,
22, 26, 28, 30,
31, 32
8
DVDD
DGND
AVDD
I
I
I
AGND
I
Analog Power Ground Pins.
OSC/REFCLK
I
Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in single-
ended mode, REFCLKB should be decoupled to AVDD with a 0.1 μF capacitor.
Reference Clock/Oscillator Input. See the Clock Input section for details on the
OSCILLATOR/REFCLK operation.
Output of the Oscillator Section.
Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low,
the oscillator section is bypassed.
This pin provides the connection for the external zero compensation network of the REFCLK
multiplier’s PLL loop filter. The network consists of a 1 k resistor in series with a 0.1 μF
capacitor tied to AVDD.
Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.
DAC Output. Should be biased through a resistor to AVDD, not AGND.
DAC Biasline Decoupling Pin.
A resistor (3.92 k nominal) connected from AGND to DAC_R
SET
establishes the reference
current for the DAC.
Input Pin Used as an External Power-Down Control (see Table 8 for details).
Active High Hardware Reset Pin. Asserting the RESET pin forces the AD9859 to the initial state,
as described in the I/O port register map.
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O
operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC
is returned low. If unused, ground this pin; do not allow this pin to float.
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output.
When operated as a 2-wire serial port, this pin is unused and can be left unconnected.
This pin functions as an active low chip select that allows multiple devices to share the I/O bus.
This pin functions as the serial data clock for I/O operations.
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only.
When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.
Digital Power Supply (for I/O Cells Only, 3.3 V).
Input Signal Used to Synchronize Multiple AD9859s. This input is connected to the SYNC_CLK
output of a master AD9859.
Clock Output Pin Serves as a Synchronizer for External Hardware.
Input Pin Used to Control the Direction of the Shaped On-Off Keying Function when
Programmed for Operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not
programmed, this pin should be tied to DGND.
The exposed paddle on the bottom of the package is a ground connection for the DAC and
must be attached to AGND in any board layout.
9
OSC/REFCLK
I
10
11
CRYSTAL OUT
CLKMODESELECT
O
I
12
LOOP_FILTER
I
20
21
23
24
IOUT
IOUT
DACBP
DAC_R
SET
O
O
I
I
35
36
PWRDWNCTL
RESET
I
I
37
IOSYNC
I
38
SDO
O
39
40
41
CS
SCLK
SDIO
I
I
I/O
43
44
DVDD_I/O
SYNC_IN
I
I
45
46
SYNC_CLK
OSK
O
I
<49>
AGND
I
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9859YSVZ | 功能描述:IC DDS DAC 10BIT 400MSPS 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9859YSVZ | 制造商:Analog Devices 功能描述:IC 400 MSPS DDS 制造商:Analog Devices 功能描述:IC, 400 MSPS DDS |
| AD9859YSVZ | 制造商:Analog Devices 功能描述:DIRECT DIGITAL SYNTHESIZER |
| AD9859YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit,1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSVZ-REEL7 | 功能描述:IC DDS DAC 10BIT 400MSPS 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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