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參數(shù)資料
| 型號： | AD9859/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/24頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9859 |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設計資源： | AD9859 Eval Brd BOM AD9859, AD9951-54 Eval Brd Gerber Files |
| 標準包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9859 |
| 主要屬性： | 10 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 400MHz 圖形用戶界面 |
| 已供物品： | 板，軟件 |
AD9859
Rev. A | Page 20 of 24
There are two phases to a communication cycle with the
AD9859. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9859, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9859 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the upcoming data
transfer is read or write and the serial address of the register
being accessed.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9859. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9859
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
register being accessed. For example, when accessing the Control
Function Register 2, which is three bytes wide, Phase 2 requires that
three bytes be transferred. If accessing the frequency tuning word,
which is four bytes wide, Phase 2 requires that four bytes be
transferred. After transferring all data bytes per the instruction,
the communication cycle is completed.
At the completion of any communication cycle, the AD9859
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. All
data input to the AD9859 is registered on the rising edge of
SCLK. All data is driven out of the AD9859 on the falling edge
of SCLK. Figure 21 through Figure 24 are useful in understand-
ing the general operation of the AD9859 serial port.
03374-0-008
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 21. Serial Port Write Timing—Clock Stall Low
03374-0-009
I6
I5
I4
I3
I2
I1
I0
DON'T CARE
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
DO 5 DO 4 DO 3 DO 2 DO 1
DO 0
DO 7
DO 6
SDO
CS
Figure 22. 3-Wire Serial Port Read Timing—Clock Stall Low
03374-0-010
I6
I5
I4
I3
I2
I1
D5
D4
D3
D2
D1
D0
I0
D7
D6
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 23. Serial Port Write Timing—Clock Stall High
03374-0-011
I6
I5
I4
I3
I2
I1
DO 5 DO 4 DO 3 DO 2 DO 1 DO 0
I0
DO 7 DO 6
I7
INSTRUCTION CYCLE
SCLK
SDIO
DATA TRANSFER CYCLE
CS
Figure 24. 2-Wire Serial Port Read Timing—Clock Stall High
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9859YSV | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 400MHz 1-DAC 10-Bit Serial 48-Pin TQFP EP 制造商:Analog Devices 功能描述:DDS 10BIT DAC 400MSPS SMD 9859 |
| AD9859YSV-REEL7 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 10-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| AD9859YSVZ | 功能描述:IC DDS DAC 10BIT 400MSPS 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9859YSVZ | 制造商:Analog Devices 功能描述:IC 400 MSPS DDS 制造商:Analog Devices 功能描述:IC, 400 MSPS DDS |
| AD9859YSVZ | 制造商:Analog Devices 功能描述:DIRECT DIGITAL SYNTHESIZER |
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