參數(shù)資料
型號: AD9858/PCBZ
廠商: Analog Devices Inc
文件頁數(shù): 19/32頁
文件大?。?/td> 0K
描述: BOARD EVAL FOR AD9858
產(chǎn)品培訓(xùn)模塊: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計資源: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
標準包裝: 1
主要目的: 計時,直接數(shù)字合成(DDS)
已用 IC / 零件: AD9858/TL
已供物品:
其它名稱: AD9858/PCB
AD9858/PCB-ND
AD9858
Rev. C | Page 26 of 32
Profile Selection
A profile consists of a specific group of memory registers (see
Table 6). In the AD9858, each profile contains a 32-bit frequency
tuning word and a 14-bit phase offset word. Each profile is
selectable via two external profile select pins (PS0 and PS1), as
defined in Table 12. The specific mapping of registers to profiles is
detailed in the Register Bit Descriptions section. The user should
be aware that selection of a profile is internally synchronized
with DDS CLK using the SYNCLK timing. That is, SYNCLK is
used to synchronize the assertion of the profile select pins (PS0
and PS1). Therefore, the PS0 and PS1 pins must be set up and
held around the rising edge of SYNCLK.
Table 12.
PS1
PS0
Profile
0
1
0
2
1
3
The profiles are available to the user to provide rapid changing
of device parameters via external hardware, which alleviates the
speed limitations imposed by the I/O port. For example, the user
might preprogram the four phase offset registers with values that
correspond to phase increments of 90°. By controlling the PS0 and
PS1 pins, the user can implement π/2 phase modulation. The data
modulation rate is much higher than that possible by repeatedly
reloading a single phase offset register via the I/O port.
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