參數(shù)資料
型號： AD9851BRSZRL
廠商： Analog Devices Inc
文件頁數(shù)： 21/24頁
文件大?。?/td> 0K
描述： IC SYNTHESR DDS/DAC 28SSOP TR
產(chǎn)品培訓模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標準包裝： 1,500
分辨率（位）： 10 b
主 fclk： 180MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 2.7 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
–6–
AD9851–Typical Performance Characteristics
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0Hz
START
72MHz
STOP
7.2MHz/
RBW = 5kHz
VBW = 5kHz
SWT = 7.2s
RF ATT = 20dB
REF LVL = –7dBm
2AP
TPC 1. Wideband (dc to 72 MHz) output SFDR for
a 1.1 MHz fundamental output signal. System
clock = 180 MHz (6 REFCLK multiplier engaged),
VS
V
V = 5 V.
S
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2AP
0Hz
START
72MHz
STOP
7.2MHz/
RBW = 5kHz
VBW = 5kHz
SWT = 7.2s
RF ATT = 20dB
REF LVL = –7dBm
TPC 2. Wideband (dc to 72 MHz) output SFDR for
a 40.1 MHz fundamental output signal. System
clock = 180 MHz (6 REFCLK multiplier engaged),
VS
V
V = 5 V.
S
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2AP
0Hz
START
72MHz
STOP
7.2MHz/
RBW = 5kHz
VBW = 5kHz
SWT = 7.2s
RF ATT = 20dB
REF LVL = –7dBm
TPC 3. Wideband (dc to 72 MHz) output SFDR for
a 70.1 MHz fundamental output signal. System
clock = 180 MHz (6 REFCLK multiplier engaged),
VS
V
V = 5 V.
S
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2AP
1.1MHz
CENTER
200kHz
SPAN
20kHz/
RBW = 300Hz
VBW = 300Hz
SWT = 11.5s
RF ATT = 20dB
REF LVL = –7dBm
TPC 4. Narrowband (1.1 ± 0.1 MHz) output SFDR
for a 1.1 MHz fundamental output signal. System
clock =180 MHz (6 REFCLK multiplier engaged),
VS
V
V = 5 V.
S
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2AP
40.1MHz
CENTER
200kHz
SPAN
20kHz/
RBW = 300Hz
VBW = 300Hz
SWT = 11.5s
RF ATT = 20dB
REF LVL = –7dBm
TPC 5. Narrowband (40.1 ± 0.1 MHz) output SFDR
for a 40.1 MHz fundamental output signal. System
clock = 180 MHz (6 REFCLK multiplier engaged),
VS
V
V = 5 V.
S
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2AP
70.1MHz
CENTER
200kHz
SPAN
20kHz/
RBW = 300Hz
VBW = 300Hz
SWT = 11.5s
RF ATT = 20dB
REF LVL = –7dBm
TPC 6. Narrowband (70.1 ± 0.1 MHz) output SFDR
for a 70.1 MHz fundamental output signal. System
clock = 180 MHz (6 REFCLK multiplier engaged),
VS
V
V = 5 V.
S
REV. D
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