參數(shù)資料
型號(hào)： AD9850BRS-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 14/20頁
文件大小： 0K
描述： IC DDS SYNTHESIZER CMOS 28-SSOP
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
標(biāo)準(zhǔn)包裝： 1,500
分辨率（位）： 10 b
主 fclk： 125MHz
調(diào)節(jié)字寬（位）： 32 b
電源電壓： 3.3V，5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 28-SSOP
包裝： 帶卷 (TR)
AD9850BRS
Parameter
Temp
Test Level
Min
Typ
Max
Unit
CMOS LOGIC INPUTS (Including CLKIN)
Logic 1 Voltage, 5 V Supply
25
°CI
3.5
V
Logic 1 Voltage, 3.3 V Supply
25
°CIV
2.4
V
Logic 0 Voltage
25
°CIV
0.8
V
Logic 1 Current
25
°CI
12
A
Logic 0 Current
25
°CI
12
A
Input Capacitance
25
°CV
3
pF
POWER SUPPLY (AOUT = 1/3 CLKIN)
+VS Current @
62.5 MHz Clock, 3.3 V Supply
Full
VI
30
48
mA
110 MHz Clock, 3.3 V Supply
Full
VI
47
60
mA
62.5 MHz Clock, 5 V Supply
Full
VI
44
64
mA
125 MHz Clock, 5 V Supply
Full
VI
76
96
mA
PDISS @
62.5 MHz Clock, 3.3 V Supply
Full
VI
100
160
mW
110 MHz Clock, 3.3 V Supply
Full
VI
155
200
mW
62.5 MHz Clock, 5 V Supply
Full
VI
220
320
mW
125 MHz Clock, 5 V Supply
Full
VI
380
480
mW
PDISS Power-Down Mode
5 V Supply
Full
V
30
mW
3.3 V Supply
Full
V
10
mW
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
TIMING CHARACTERISTICS*
AD9850BRS
Parameter
Temp
Test Level
Min
Typ
Max
Unit
tDS (Data Setup Time)
Full
IV
3.5
ns
tDH (Data Hold Time)
Full
IV
3.5
ns
tWH (W_CLK Minimum Pulse Width High)
Full
IV
3.5
ns
tWL (W_CLK Minimum Pulse Width Low)
Full
IV
3.5
ns
tWD (W_CLK Delay after FQ_UD)
Full
IV
7.0
ns
tCD (CLKIN Delay after FQ_UD)
Full
IV
3.5
ns
tFH (FQ_UD High)
Full
IV
7.0
ns
tFL (FQ_UD Low)
Full
IV
7.0
ns
tCF (Output Latency from FQ_UD)
Frequency Change
Full
IV
18
CLKIN Cycles
Phase Change
Full
IV
13
CLKIN Cycles
tFD (FQ_UD Minimum Delay after W_CLK)
Full
IV
7.0
ns
tRH (CLKIN Delay after RESET Rising Edge)
Full
IV
3.5
ns
tRL (RESET Falling Edge after CLKIN)
Full
IV
3.5
ns
tRS (Minimum RESET Width)
Full
IV
5
CLKIN Cycles
tOL (RESET Output Latency)
Full
IV
13
CLKIN Cycles
tRR (Recovery from RESET)
Full
IV
2
CLKIN Cycles
Wake-Up Time from Power-Down Mode
25
°CV
5
s
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
(VS = 5 V
5% except as noted, RSET = 3.9 k )
REV. H
–3–
AD9850
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