參數(shù)資料
型號(hào): AD9846AJST
廠商: ANALOG DEVICES INC
元件分類: 消費(fèi)家電
英文描述: Complete 10-Bit 30 MSPS CCD Signal Processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: PLASTIC, LQFP-48
文件頁數(shù): 10/24頁
文件大?。?/td> 231K
代理商: AD9846AJST
REV. 0
AD9846A
–10–
PIXEL GAIN AMPLIFIER (
PxGA
) TIMING
FRAME n
VD
HD
LINE 0
LINE 1
LINE 2
LINE m
0101...
2323...
0101...
LINE m
1
LINE 0
LINE 1
LINE 2
LINE m
0101...
2323...
0101...
LINE m
1
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
FRAME n+1
Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence
SHP
HD
3ns MIN
3ns MIN
PxGA
GAIN
GAIN0
GAIN1
GAIN0
GAIN3
GAIN2
GAINX
GAINX
VD
NOTES:
1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.
2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.
3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.
4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
5 PIXEL MIN
Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing
0101...
2323...
0101...
0101...
2323...
0101...
HD
LINE 0
LINE 1
LINE 2
LINE m
LINE m
1
LINE 0
LINE 1
LINE 2
LINE m
LINE m
1
EVEN FIELD
ODD FIELD
NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
VD
Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence
NOTES:
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.
3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.
SHP
HD
PxGA
GAIN
3ns MIN
3ns MIN
5 PIXEL MIN
VD
GAIN0
GAIN1
GAIN0
GAIN3
GAIN2
GAINX
GAINX
Figure 11. PxGA Mode 2 (Interlace) Detailed Timing
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