參數(shù)資料
型號(hào)： AD9814JR
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/15頁(yè)
文件大?。?/td> 0K
描述： IC CCD SIGNAL PROC 14BIT 28-SOIC
標(biāo)準(zhǔn)包裝： 27
類型： CCD 信號(hào)處理器，14 位
輸入類型： 邏輯
輸出類型： 邏輯
接口： 3 線串口
電流 - 電源： 80mA
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
REV. 0
–13–
AD9814
Figure 12 shows how the OFFSET pin may be used in a CIS
application for coarse offset adjustment. Many CIS signals have
dc offsets ranging from several hundred millivolts to more than
1 V. By connecting the appropriate dc voltage to the OFFSET
pin, the CIS signal will be restored to “zero.” After the large dc
offset is removed, the signal can be scaled using the PGA to
maximize the ADC’s dynamic range.
AD9814
OFFSET
RED-OFFSET
GREEN-OFFSET
BLUE-OFFSET
VINR
VING
VINB
RED
GREEN
BLUE
0.1 F
AVDD
VREF FROM
CIS MODULE
DC OFFSET
R1
R2
SHA
Figure 12. SHA-Mode Used with External DC Offset
Programmable Gain Amplifiers
The AD9814 uses one Programmable Gain Amplifier (PGA) for
each channel. Each PGA has a gain range from 1x (0 dB) to
5.8x (15.5 dB), adjustable in 64 steps. Figure 6 shows the PGA
gain as a function of the PGA register code. Although the gain
curve is approximately “l(fā)inear in dB”, the gain in V/V varies
nonlinearly with register code, following the equation:
Gain
G
=
+
58
14 8
63
.
where G is the decimal value of the gain register contents, and
varies from 0 to 63.
PGA REGISTER VALUE – Decimal
15
0
GAIN
–
dB
(
)
12
9
6
3
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 63
6.0
5.0
4.0
3.0
2.0
1.0
GAIN
–
V/V
(
)
Figure 13. PGA Gain Transfer Function
0
2000
4000
6000
8000
10000 12000 14000
16383
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
DNL GRAPH
MAX DNL +0.48
MIN DNL –0.39
5.0
4.0
3.0
2.0
1.0
0.0
–1.0
–2.0
–3.0
–4.0
–5.0
0
2000
4000
6000
8000
10000 12000 14000
16383
INL GRAPH
MAX INL +1.22
MIN INL –4.06
LSB
Figure 14. Typical Linearity Performance
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