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參數(shù)資料
| 型號(hào)： | AD9803 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD And Video Signal Processor For Electronic Cameras(電子照相機(jī)的CCD信號(hào)和視頻信號(hào)處理器) |
| 中文描述： | CCD及視頻信號(hào)處理器電子相機(jī)（電子照相機(jī)的防治荒漠化公約信號(hào)和視頻信號(hào)處理器） |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大?。?/td> | 105K |
| 代理商： | AD9803 |
AD9803
–10–
REV. PrA
PTCNCL
DT
RISING EDGE
TRIGGERED
t
DH
t
LS
t
LH
REGISTER LOADED ON
RISING EDGE
RNW
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
SDATA
SCK
SL
t
DS
Figure 34. Serial WRITE Operation
SDATA
RNW
A0
A1
A2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
XX
XX
DUMMY BITS
IGNORED
SCK
SL
Figure 35. 16-Bit Serial WRITE Operation
NOTE
:
With the exception of a write to the PGA register during
AUX-mode, all data writes must be 10 bits. During an AUX-
mode write to the PGA register, only 8 bits of data are re-
quired. If more than 14 SCK rising edges are applied during a
write operation, additional SCK pulses will be ignored (see
Figure 35). All reads must be 10 bits to receive valid register
contents. All registers default to 0s on power-up, except for the
A-register, which defaults to 11. Thus, on power-up, the AD9803
defaults to CCD mode. During the power-up phase, it is recom-
mended that SL be HIGH and SCK be LOW to prevent acci-
dental register write operations. SDATA may be unknown. The
RNW bit (“Read/Not Write”) must be LOW for all write opera-
tions to the serial interface, and HIGH when reading back from
the serial interface registers.
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