參數(shù)資料
型號(hào)： AD9787BSVZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 40/64頁(yè)
文件大小： 0K
描述： IC DAC 14BIT 800MSPS 100TQFP
產(chǎn)品培訓(xùn)模塊： Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝： 1,000
系列： TxDAC®
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 2
電壓電源： 模擬和數(shù)字
功率耗散（最大）： 450mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP-EP（14x14）
包裝： 帶卷 (TR)
輸出數(shù)目和類型： 4 電流，單極；4 電流，雙極
采樣率（每秒）： 800M
AD9785/AD9787/AD9788
Rev. A | Page 45 of 64
Table 32 shows the register settings required to enable the pulse
mode synchronization feature.
Table 32. Register Settings for Enabling Pulse Sync Mode
Register
Bit
Parameter
Value
0x01
[13]
PN code sync enable
0
[12]
Sync mode select
0
[11]
Pulse sync enable
1
0x03
[26]
SYNC_I enable
1
[25]
SYNC_O enable
0
[10]
Set high
1
Synchronization Timing Error Detection
The synchronization logic has error detection circuitry similar
to the input data timing. The Sync Timing Margin [3:0] variable
(Register 0x03) determines the setup and hold margin that the
synchronization interface needs for the SYNC timing error IRQ
to remain inactive (show error-free operation). Thus, the SYNC
timing error IRQ is set whenever the setup and hold margins
drop below the Sync Timing Margin [3:0] value and does not
necessarily indicate that the SYNC_I input was latched incorrectly.
When a SYNC timing error IRQ is set, corrective action can
restore the timing margin. The device can be configured for
manual mode sync error monitoring and error correction.
Follow these steps to monitor SYNC_I setup and hold timing
margins in manual mode:
1.
Set sync error check mode (Register 0x03, Bit 18) = 0
(manual check mode).
2.
Set Sync Timing Margin [3:0] (Register 0x03, Bits [3:0]) =
0000 (timing margin to minimum value).
3.
Set SYNC_I Delay [4:0] (Register 0x03, Bits [23:19]) =
00000 (SYNC_I delay line to minimum value).
4.
Set sync port IRQ enable (Register 0x09, Bit 0) = 1.
5.
Write 1 to sync timing error IRQ (Register 0x09, Bit 6)
to clear.
6.
Read back sync timing error IRQ and sync timing error
type (Register 0x09, Bit 4). If sync timing error IRQ is high,
a sampling error has occurred, and sync timing error type
indicates whether the sampling error is due to a setup time
violation or a hold time violation.
7.
Adjust the SYNC_I Delay [4:0] value until the sync timing
error IRQ is no longer present.
SYNCHRONIZING MULTIPLE DEVICES TO EACH
OTHER
The AD9785/AD9787/AD9788 synchronization engine uses
a PN code synchronization scheme to align multiple devices
within a system to the same DAC clock edge. The PN code
scheme synchronizes all the internal clocks, as well as the phase
accumulator of the NCO for all devices. With this scheme, one
device functions as the master, and the remainder of the devices
are configured as slaves.
The master device generates the PN encoded signal and drives
the signal out on the SYNC_O (SYNC_O+/SYNC_O) output
pins. This signal is then sent to the SYNC_I (SYNC_I+/
SYNC_I) inputs of all the slave devices and to itself. The slave
devices receive the code from the master and demodulate the
signal to produce a synchronization pulse every time a valid
code is received. The encoded signal of every device must be
sampled on the same DAC clock edge for the devices to be
properly synchronized. Therefore, it is extremely important that
the REFCLK signals arrive at all the devices with as little skew
between them as possible. In addition, the SYNC_I signals must
arrive at all the devices with as little skew as possible. At high
DACCLK frequencies, this requires using low skew clock
distribution devices to deliver the REFCLK and SYNC_I signals
and paying careful attention to printed circuit board signal
routing to equalize the trace lengths of these signals.
07
09
8-
1
03
SYSTEM CLOCK
LOW SKEW
CLOCK DRIVER
LOW SKEW
CLOCK DRIVER
MATCHED
LENGTH TRACES
MATCHED
LENGTH TRACES
REFCLK
TXENABLE
SYNC_I
REFCLK
TXENABLE
SYNC_I
OUT
SYNC_O
Figure 64. Multichip Synchronization in PN Code Mode
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