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參數(shù)資料
| 型號： | AD9787BSVZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 47/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 800MSPS 100TQFP |
| 產品培訓模塊： | Data Converter Fundamentals DAC Architectures |
| 標準包裝： | 1 |
| 系列： | TxDAC® |
| 位數(shù)： | 14 |
| 數(shù)據接口： | 串行 |
| 轉換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 450mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-TQFP 裸露焊盤 |
| 供應商設備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | 4 電流，單極；4 電流，雙極 |
| 采樣率（每秒）： | 800M |
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AD9785/AD9787/AD9788
Rev. A | Page 51 of 64
There are two output signals on each auxiliary DAC. One signal
is designated P, the other N. The sign bit in each auxiliary DAC
control register (Bit 15) controls whether the P side or the N side
of the auxiliary DAC is turned on. Only one side of the auxiliary
DAC is active at a time. The auxiliary DAC structure is shown
07
09
8-
0
32
AUX_P
AUX_N
P/N
SOURCE/
SINK
0TO 2mA
(SINK)
VBIAS
0TO 2mA
(SOURCE)
Figure 71. Auxiliary DAC Structure
The magnitude of the auxiliary DAC 1 current is controlled by
the auxiliary DAC 1 control register (Register 0x06), and the
magnitude of the auxiliary DAC 2 current is controlled by the
auxiliary DAC 2 control register (Register 0x08). These auxiliary
DACs have the ability to source or sink current. This selection is
programmable via Bit 14 in either auxiliary DAC control register.
The choice of sinking or sourcing should be made at circuit
design time. There is no advantage to switching between
sourcing and sinking current after the circuit is in place.
The auxiliary DACs can be used for local oscillator (LO) cancel-
lation when the DAC output is followed by a quadrature modu-
lator. This LO feedthrough is caused by the input referred dc
offset voltage of the quadrature modulator (and the DAC output
offset voltage mismatch) and can degrade system performance.
Typical DAC-to-quadrature modulator interfaces are shown in
Figure 72 and Figure 73. Often, the input common-mode
voltage for the modulator is much higher than the output
compliance range of the DAC, so that ac coupling or a dc level
shift is necessary. If the required common-mode input voltage
on the quadrature modulator matches that of the DAC, then the
dc blocking capacitors in Figure 72 can be removed.
A low-pass or band-pass passive filter is recommended when
spurious signals from the DAC (distortion and DAC images) at
the quadrature modulator inputs can affect system performance.
Placing the filter at the location shown in Figure 72 and Figure 73
allows easy design of the filter, as the source and load impedances
can easily be designed close to 50 Ω.
Q DAC
AUX
DAC2
25 TO 50
0.1F
OPTIONAL
PASSIVE
FILTERING
QUADRATURE
MODULATOR V+
QUAD MOD
Q INPUTS
I DAC
AUX
DAC1
25 TO 50
0.1F
OPTIONAL
PASSIVE
FILTERING
QUADRATURE
MODULATOR V+
QUAD MOD
I INPUTS
07
09
8-
0
33
Figure 72. Typical Use of Auxiliary DACs AC Coupling to Quadrature Modulator
07
09
8-
11
5
I OR Q DAC
25 TO 50
OPTIONAL
PASSIVE
FILTERING
AUX
DAC1 OR
DAC2
QUAD MOD
I AND Q INPUTS
Figure 73. Typical Use of Auxiliary DACs DC Coupling to Quadrature Modulator with DC Shift
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| AD9788BSVZ | 功能描述:IC DAC 16BIT 800MSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據采集 - 數(shù)模轉換器 系列:TxDAC® 產品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:50 系列:- 設置時間:4µs 位數(shù):12 數(shù)據接口:串行 轉換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應商設備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產品目錄頁面:1398 (CN2011-ZH PDF) |
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