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參數(shù)資料
| 型號(hào)： | AD9786 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 200 MSPS/500 MSPS TxDAC+ with 2】/4】/8】 Interpolation and Signal Processing |
| 中文描述： | 16位，200 MSPS/500 MSPS的TxDAC系列2】/ 4】/ 8】插值與信號(hào)處理 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大?。?/td> | 1497K |
| 代理商： | AD9786 |
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AD9786
AD9786 DATACLK Slave Mode, Data Recovery On
Rev. 0 | Page 28 of 60
DATACLK (Pin 31) can be used as an input in order to
synchronize multiple AD9786s. A clock generated by an
AD9786 operating in master mode, or a clock from an external
source, can be used to drive DATACLK.
In this mode, there are two clocks required to be applied to the
AD9786. A clock running at the DAC sample rate, referred to as
DACCLK, must be applied to the differential inputs (Pins 5 and
6) of the AD9786. As described above, a clock at the input
sample rate must also be applied to Pin 31 (DATACLK). An
internal DLL synchronizes the two applied clocks. The timing
relationships between the input data, DATACLK, and DACCLK
are given in Figure 49 and Figure 50.
Note that DCLKPOL (Reg 02h, Bit 4) can be used to select the
edge of DACCLK upon which the input data is latched.
There is a defined setup and hold window with respect to input
data and the latching edge of DACCLK. There is also a required
timing relationship between DATACLK and DACCLK. This is
referred to in Figure 49 and Figure 50 as t
ST
and t
HT
(setup and
hold for transition). As an example, with DCLKPOL set to
logic 0, the input data will latch on the first rising edge of
DACCLK which occurs greater than 1.5 ns before the falling
edge of DATACLK. DACCLK should not be given a rising edge
in the window of 500 ps to 1.5 ns before the latching edge
(falling when DCLKPOL = 0, rising when DCLKPOL = 1) of
DATACLK. Failure to account for this timing relationship may
result in corrupt data.
There are three status bits available for read which allow the
user to verify DLL lock. These are Bits 0, 1, and 2 (DCRCSTAT)
in Reg 12h.
0
DACCLK
IN
DATACLK
IN
DATA
t
HT
= 1.5ns MIN
t
S
= 0.0ns MIN
t
ST
= –500ps MIN
t
H
= 3.2ns MIN
Figure 49. Slave Mode Timing, 2× Interpolation, DCLKPOL = 0
0
DACCLK
IN
DATACLK
IN
DATA
t
HT
= 2.0ns MIN
t
S
= 0.0ns MIN
t
ST
= –1.0ns MIN
t
H
= 3.2ns MIN
Figure 50. Slave Mode Timing, 2× Interpolation, DCLKPOL = 1
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