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參數(shù)資料
| 型號： | AD977ACN |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 16-Bit, 100 kSPS/200 kSPS BiCMOS A/D Converter |
| 中文描述： | 3-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP20 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-20 |
| 文件頁數(shù)： | 11/24頁 |
| 文件大?。?/td> | 284K |
| 代理商： | AD977ACN |
AD977/AD977A
–11–
REV. D
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION WITH SYNC OUTPUT
GENERATED
Figure 7 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either
CS
is High or while both
CS
and R/
C
are low. In Figure 7 a conversion is initiated by taking R/
C
low
with
CS
tied low. While this condition exists a transition of
DATACLK, clock pulse #0, will enable the generation of a
SYNC pulse. Less then 83 ns after R/
C
is taken low the
BUSY
output will go low to indicate that the conversion process has
began. Figure 7 shows R/
C
then going high and after a delay of
greater than 15 ns (t
15
) clock pulse #1 can be taken high to
request the SYNC output. The SYNC output will appear
approximately 40 ns after this rising edge and will be valid on
the falling edge of clock pulse #1 and the rising edge of clock
pulse #2. The MSB will be valid approximately 40 ns after the
rising edge of clock pulse #2 and can be latched off either the
falling edge of clock pulse #2 or the rising edge of clock pulse
#3. The LSB will be valid on the falling edge of clock pulse #17
and the rising edge of clock pulse #18. Approximately 40 ns
after the rising edge of clock pulse #18, the DATA output
pin will reflect the state of the TAG input pin during the
rising edge of clock pulse #2.
BUSY
R/C
EXT
DATACLK
t
13
BIT 15
(MSB)
BIT 14
1
2
DATA
SYNC
t
14
t
12
0
3
17
18
t
2
t
17
BIT 0
(LSB)
TAG 0
TAG 1
TAG 0
TAG 1
TAG 2
TAG 16
TAG 17
TAG 18
t
18
TAG 19
TAG
TAG 2
4
t
15
t
15
t
15
t
12
t
18
t
24
t
23
Figure 6. Conversion and Read Timing Using An External Discontinuous Data Clock (EXT/
INT
Set to Logic High,
CS
Set
to Logic Low)
BUSY
R/C
EXT
DATACLK
t
13
t
15
BIT 15
(MSB)
BIT 14
1
2
DATA
SYNC
t
14
t
12
0
3
18
t
1
t
12
BIT 0
(LSB)
TAG 0
t
22
t
15
t
20
t
2
t
17
t
18
t
18
Figure 7. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using External
Discontinuous Data Clock (EXT/
INT
Set to Logic High,
CS
Set to Logic Low)
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