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參數(shù)資料
| 型號(hào)： | AD9774ASZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT 32MSPS 44MQFP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 800 |
| 系列： | TxDAC+® |
| 設(shè)置時(shí)間： | 35ns |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 1.13W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-QFP |
| 供應(yīng)商設(shè)備封裝： | 44-MQFP（10x10） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 2 電流，單極；2 電流，雙極 |
| 采樣率（每秒）： | 32M |
AD9774
–7–
REV. B
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight
line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected
when all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s, minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25
°C) value to the value at either T
MIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is re-
ported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal. It is
expressed as a percentage or in decibels (dB).
Signal-to-Noise Ratio (SNR)
S/N is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Passband
Frequency band in which any input applied therein passes
unattenuated to the DAC output.
Stopband Rejection
The amount of attenuation of a frequency outside the passband
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the passband.
Group Delay
Number of input clocks between an impulse applied at the
device input and peak DAC output current.
Impulse Response
Response of the device to an impulse applied to the input.
VCO
IN/EXT
PLL
DIVIDE
PLLCOM
REFLO
PLL CLOCK
MULTIPLIER
REFIO
CLK
IN/OUT
SNOOZE
IOUTA
FSADJ
AD9774
SLEEP
DCOM DVDD ICOMP ACOM AVDD
+1.2V REFERENCE
AND CONTROL AMP
PLL
ENABLE
PLLLOCK
CLK4 IN
PLLVDD
LPF
IOUTB
EDGE
TRIGGERED
LATCHES
14-BIT DAC
2
1
2
4
14
DIGITAL
DATA
TEKTRONIX
AWG-2021
50
20pF
50
20pF
0.1 F
100
MINI-CIRCUITS
T1-1T
TO HP3589A
SPECTRUM / NETWORK
ANALYZER
50
INPUT
0.01 F
1.5k
+3VD
0.1 F
+5VA
1.91k
0.1 F
REFCOMP
OPTION
4
Figure 3. Basic AC Characterization Test Setup
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