參數(shù)資料
型號(hào): AD9774AS
廠商: ANALOG DEVICES INC
元件分類: DAC
英文描述: 14-Bit, 32 MSPS TxDAC⑩ with 4x Interpolation Filters
中文描述: PARALLEL, WORD INPUT LOADING, 0.035 us SETTLING TIME, 14-BIT DAC, PQFP44
封裝: METRIC, QFP-44
文件頁數(shù): 12/24頁
文件大?。?/td> 313K
代理商: AD9774AS
AD9774
–12–
REV. B
+2.7 TO +5.5V
A
0.1
m
F
1.20V REF
REFLO
AVDD
ACOM
ICOMP
0.1
m
F
LSB
SWITCHES
SEGMENTED
SWITCHES
1.91k
V
IOUTA
IOUTB
CURRENT
SOURCE
ARRAY
REFIO
FS ADJ
0.1
m
F
50pF
AD9774
REFCOMP
Figure 26. Block Diagram of Internal DAC, 1.2 V Reference,
and Reference Control Circuits
The full-scale output current is regulated by the reference con-
trol amplifier and can be set from 2 mA to 20 mA via an exter-
nal resistor, R
SET
. The external resistor, in combination with
both the reference control amplifier and voltage reference,
REFIO, sets the reference current, I
REF
, which is mirrored over
to the segmented current sources with the proper scaling factor.
The full-scale current, I
OUTFS
, is exactly thirty-two times the
value of I
REF
.
DAC TRANSFER FUNCTION
The AD9774 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current out-
put, I
OUTFS
, when all bits are high (i.e., DAC CODE = 16383)
while IOUTB, the complementary output, provides no current.
The current output appearing at IOUTA and IOUTB is a func-
tion of both the input code and I
OUTFS
and can be expressed as:
IOUTA
= (
DAC CODE
/16384)
×
I
OUTFS
IOUTB
= (16383 –
DAC CODE
)/16384
×
I
OUTFS
where
DAC CODE
= 0 to 16383 (i.e., Decimal Representation).
As previously mentioned, I
OUTFS
is a function of the reference
current I
REF
, which is nominally set by a reference voltage
V
REFIO
and external resistor R
SET
. It can be expressed as:
I
OUTFS
= 32
×
I
REF
where
I
REF
=
V
REFIO
/
R
SET
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, R
LOAD
, that are tied to analog common, ACOM. Note
that R
LOAD
may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50
or 75
cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply:
V
OUTA
=
IOUTA
×
R
LOAD
V
OUTB
=
IOUTB
×
R
LOAD
Note that the full-scale value of V
OUTA
and V
OUTB
should not
exceed the specified output compliance range to maintain speci-
fied distortion and linearity performance.
The differential voltage, V
DIFF
, appearing across IOUTA and
IOUTB is:
V
DIFF
= (
IOUTA – IOUTB
)
×
R
LOAD
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Substituting the values of IOUTA, IOUTB and I
REF
; V
DIFF
can
be expressed as:
V
DIFF
= {(2
DAC CODE
– 16383)/16384}
×
V
DIFF
= {
(32
R
LOAD
/
R
SET
)
×
V
REFIO
These last two equations highlight some of the advantages of
operating the AD9774 differentially. First, the differential
operation will help cancel common-mode error sources associ-
ated with IOUTA and IOUTB such as noise, distortion and dc
offsets. Second, the differential code-dependent current and
subsequent voltage, V
DIFF
, is twice the value of the single-ended
voltage output (i.e., V
OUTA
or V
OUTB
), thus providing twice the
signal power to the load.
Note that the gain drift temperature performance for a single-
ended (VOUTA and VOUTB) or differential output (V
DIFF
) of
the AD9774 can be enhanced by selecting temperature tracking
resistors for R
LOAD
and R
SET
due to their ratiometric relation-
ship as shown in Equation 8.
(8)
REFERENCE OPERATION
The AD9774 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external
reference. REFIO serves as either an
input
or
output,
depending
on whether the internal or external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 27, the internal
reference is activated, and REFIO provides a 1.20V output. In
this case, the internal reference
must
be compensated externally
with a ceramic chip capacitor of 0.1
μ
F or greater from REFIO
to REFLO. If any additional loading is required, REFIO should
be buffered with an external amplifier having an input bias cur-
rent less than 100 nA.
50pF
+1.2V REF
AVDD
REFLO
CURRENT
SOURCE
ARRAY
+2.7 TO +5.5V
A
REFIO
FSADJ
2k
V
0.1
m
F
AD9774
ADDITIONAL
LOAD
OPTIONAL
EXTERNAL
REF BUFFER
0.1
m
F
REFCOMP
Figure 27. Internal Reference Configuration
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may then be applied
to REFIO as shown in Figure 28. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1
μ
F compensation capacitor is not required
since the internal reference is disabled, and the high input im-
pedance (i.e., 1 M
) of REFIO minimizes any loading of the
external reference.
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